US3906153A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Remote synchronous loop operation over half-duplex communications link
Assignee: International Business Machines Corp
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Filing: 1973-12-26
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Granted: 1975-09-16
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Expires: 1993-12-26
Abstract
Abstract A remote synchronous loop which operates in the manner disclosed in U.S. Pat. No. 3,752,932 is connected to a central control unit by a local interface unit and a half-duplex communications link. The local interface unit provides an interface between the halfduplex link and the loop and has four modes of operation. These modes are stand by, receive, turn-around and transmit. During stand-by mode, the devices on the loop are neither receiving or transmitting data and the local interface unit provides clocking and synchronization signals for the devices on the loop. During receive mode, the local interface unit provides for gradual synchronization of the loop devices to the received data clock without loss of data. During turn-around mode which occurs between receive and transmit, the local interface unit maintains synchronization of the remote loop devices and enables transmission when the half-duplex link is clear. During transmit mode, the interface unit enables the remote loop devices and passes the received data from the loop to the half-duplex link. This mode is entered from the turn-around mode after the halfduplex link is clear.
Inventors
- 👤 Alexande Polischuk-Sawtschenko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:06
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/423
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
317 words
An interface unit located at a remote synchronous serial data communications loop for connecting a central station to the remote synchronous serial data communications loop via a halfduplex data communications link and in which said remote loop may assume a transmit mode in which data from the devices on the loop are sent via the half-duplex link to the central station and a receive mode in which data signals from the central station are received via the half-duplex link and transferred to the devices on the loop comprising: a first circuit means for generating first clocking signals at a predetermined frequency; a second circuit means for generating second clocking signals at said predetermined frequency in synchronism with the signals received from said half-duplex communications link; clock control means responsive to the signals received from said half-duplex communications link and said second clocking signals for simultaneously incrementally adjusting the phase of the first and second clock signal generating means to cause said first and second clocking signals to gradually assume a predetermined phase relationship with respect to the phase of the signals received from said half-duplex communications link; a first buffer means for receiving data signals from said half-duplex communications link under control of second clocking signals; a second buffer means for receiving data signals from said first buffer means under control of said first clocking signals; signal generating means for generating control signals under control of said first clocking signals; and control circuit means responsive to signals received from said half-duplex communications link for transmitting the contents of said second buffer means to the loop when data signals are being received from said half-duplex communications link and for transmitting said control signals from said signal generating means when data signals are not being received whereby said devices on said loop are maintained in synchronism at all times regardless of the direction of transmission on said half-duplex link.
Claim 2
Dependent Claim
317 words
An interface unit located at a remote synchronous serial data communications loop for connecting a central station to the remote synchronous serial data communications loop via a halfduplex data communications link and in which said remote loop may assume a transmit mode in which data from the devices on the loop are sent via the half-duplex link to the central station and a receive mode in which data signals from the central station are received via the half-duplex link and transferred to the devices on the loop comprising: a first circuit means for generating first clocking signals at a predetermined frequency; a second circuit means for generating second clocking signals at said predetermined frequency in synchronism with the signals received from said half-duplex communications link; clock control means responsive to the signals received from said half-duplex communications link and said second clocking signals for simultaneously incrementally adjusting the phase of the first and second clock signal generating means to cause said first and second clocking signals to gradually assume a predetermined phase relationship with respect to the phase of the signals received from said half-duplex communications link; a first buffer means for receiving data signals from said half-duplex communications link under control of second clocking signals; a second buffer means for receiving data signals from said first buffer means under control of said first clocking signals; signal generating means for generating control signals under control of said first clocking signals; and control circuit means responsive to signals received from said half-duplex communications link for transmitting the contents of said second buffer means to the loop when data signals are being received from said half-duplex communications link and for transmitting said control signals from said signal generating means when data signals are not being received whereby said devices on said loop are maintained in synchronism at all times regardless of the direction of transmission on said half-duplex link.
Claim 3
Dependent Claim
22 words
An interface unit as set forth in claim 1 in which said first and second clocking signals have a predetermined phase difference.
Claim 4
Dependent Claim
24 words
An interface unit as set forth in claim 2 in which said first and second buffer means receive and store a single data signal.
Claim 5
Dependent Claim
45 words
An interface unit as set forth in claim 2 in which said second circuit means for generating said second clocking signals is inhibited while no signals are received from said half-duplex communications link and is started when signals are received from the half-duplex communications link.
Claim 6
Dependent Claim
63 words
An interface unit as set forth in claim 4 in which said first and second circuit means for generating said first and second clocking signals each include a common source of pulsating electric signals and gate means under control of said clock control means for controlling the number of pulses applied to the noncommon elements of the said first and second circuit means.
Claim 7
Dependent Claim
87 words
An interface unit as set forth in claim 5 in which said clock control means includes means for comparing the phase of signals received from said half-duplex communications link with the phase of said second clocking signals to provide control signals for controlling the common gatE means to advance or retard said first and second circuit means by a predetermined amount to cause the phase of the first and second clocking signals to gradually assume a predetermined relationship to the signals received from the half-duplex communications link.
Claim 8
Dependent Claim
77 words
An interface unit as set forth in claim 6 in which said common source of pulsating signals has a frequency substantially higher than the frequency of the signals received from said half-duplex communications link and said clock control means includes circuit means responsive to the control signals generated by said comparison means to limit the control exercised over the common gate means whereby correction of the phase of said first and second clocking signals is gradually achieved.
References Cited (Backward Citations)
US3544976A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-09-15 | 1979-03-17 | 1979-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-09-15 | 1983-03-17 | 1983-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-09-15 | 1987-03-17 | 1987-09-16 | $7700.00 | Window Closed / Lapsed |