Control system for electronic PABX switching matrix

Claim 2

In an electronic telephone system including a plurality of line circuits, a plurality of junctor circuits and a switching network connected to said line circuits and junctor circuits in the form of a matrix of input lines and output lines interconnected at their crosspoints by respective crosspoint switches which are reset upon application of an addressing signal thereto and set upon application of both an addressing signal and a control signal thereto, matrix control means for controlling said crosspoint switches to selectively connect a line circuit to a junctor circuit and to another line circuit comprising line scanner means for generating sequential line address signals corresponding to said line circuits, and line selector means responsive to said line scanner means for applying addressing signals to all crosspoints switches connected to an input line of said switching network which is connected to a line circuit identified by each line address signal.

Claim 3

The system defined in claim 1, wherein said line selector means includes decoder means responsive to each line address signal for generating said crosspoint switch addressing signals corresponding to the particular line address.

Claim 4

The system defined in claim 2, wherein said matrix is a solid state matrix of saturated transistor crosspoint switches.

Claim 5

The system defined in claim 2, further including junctor memory means having a memory position assigned to each junctor circuit for storing therein line address signals identifying each line circuit to be connected to respectiVe junctor circuit through said switching network, and means for sequentially applying said line address signals stored in said junctor memory means to said line selector means to effect application of addressing signals to the crosspoint switches interconnnecting the input and output lines of the matrix connected to the designated line circuit and junctor circuit.

Claim 6

The system defined in claim 4, wherein said line selector means includes selector switch means for selectively applying said line address signals from said line scanner means and said junctor memory means in sequence to said decoder means.

Claim 7

The system defined in claim 5, further including crosspoint control means for generating control signals in connection with selected crosspoint switches to set said switches as they are addressed by said line selector means.

Claim 8

The system defined in claim 6, further including status means for storing data representing the status of each line circuit connection for the line circuits connected to each junctor and control circuit means responsive to the data stored in said status means for controlling said crosspoint control means to set selected crosspoint switches in said switching network.

Claim 9

The system defined in claim 7, further including clock means for controlling said line selector means and said junctor memory means to scan all memory positions of said junctor memory means inbetween each advance of said line scanner means in its generation of line address signals.

Claim 10

The system defined in claim 8, wherein said crosspoint control means is responsive to said clock means for generating timing control signals for operating said selector switch means in said line selector means.

Claim 11

In an electronic telephone system including a plurality of line circuits, a plurality of junctor circuits and a switching network connected to said line circuits and junctor circuits in the form of a matrix of input lines and output lines interconnected at their crosspoints by respective crosspoint switches which are reset upon application of an addressing signal thereto and set upon application of both an addressing signal and a control signal thereto, matrix control means for controlling said crosspoint switches to selectively connect a line circuit to a junctor circuit and to another line circuit comprising junctor memory means having a memory position assigned to each junctor circuit for storing therein line address signals identifying each line circuit connected to a respective junctor circuit through said switching network, line selector means responsive to line address signals from said junctor memory means for applying addressing signals to the crosspoint switches interconnecting the input and output lines of the matrix connected to the line circuit and junctor circuit designated by the line address signal and the memory position from which it is derived.

Claim 12

In an electronic telephone system including a plurality of line circuits, a plurality of junctor circuits and a switching network connected to said line circuits and junctor circuits in the form of a matrix of input lines and output lines interconnected at their crosspoints by respective crosspoint switches which are reset upon application of an addressing signal thereto and set upon application of both an addressing signal and a control signal thereto, matrix control means for controlling said crosspoint switches to selectively connect a line circuit to a junctor circuit and to another line circuit comprising junctor memory means having a memory position assigned to each junctor circuit for storing therein line address signals identifying each line circuit connected to a respective junctor circuit through said switching network, line selector means responsive to line address signals from said junctor memory means for applying addressing signals to the crosspoint switches interconnecting the input and output lines of the matrix connected to the line circuit and junctor circuit designated by the line address signal and the memory position from which it is derived.

Claim 13

The system defined in claim 10, further including crosspoint control means for generating control signals in connection with selected crosspoint switches to set said switches as they are addressed by said line selector means.

Claim 14

The system defined in claim 11, further including status means for storing data representing the status of each line circuit connection for the line circuits connected to each junctor and control circuit means responsive to the data stored in said status means for controlling said crosspoint control means to set selected crosspoint switches in said switching network.

Claim 15

The system defined in claim 12, wherein said line selector means includes decoder means responsive to each line address signal for generating said crosspoint switch addressing signals corresponding to the particular line address.

Claim 16

The system defined in claim 12, wherein said matrix is a solid state matrix of saturated transistor crosspoint switches.

Claim 17

The system defined in claim 13, further including line scanner means for sequentially generating line address signals corresponding to each of said line circuiTs, and means for applying said line address signals from said line scanner means to said line selector means for addressing as a group all crosspoint switches connectd to a common input line in the order of the line circuits connected thereto.

Claim 18

The system defined in claim 15, wherein said line selector means includes selector switch means for selectively applying said line address signals from said line scanner means and said junctor memory means in sequence to said decoder means.

Claim 19

The system defined in claim 16, further including clock means for controlling said line selector means and said junctor memory means to scan all memory positions of said junctor memory means inbetween each advance of said line scanner means in its generation of line address signals.

Claim 20

The system defined in claim 17, wherein said crosspoint control means is responsive to said clock means for generating timing control signals for operating said selector switch means in said line selector means.