US3902017A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ringer guard circuitry for subscriber carrier telephone system
Assignee: AG Communication Systems Corp
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Filing: 1974-01-25
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Granted: 1975-08-26
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Expires: 1994-01-25
Abstract
Abstract The ringer guard circuit operates from either tip-grounded or ring-grounded central office ringing signals by coupling a portion thereof between ground and the center tap of a resistive divider that is connected across the tip and ring lines of the central office drop. The guard circuit alternately connects a supply voltage to a carrier oscillator through a control transistor and disconnects the supply voltage from the oscillator during positive and negative half cycles, respectively, of coupled ringing signals with magnitudes that are greater than a prescribed threshold value. A depletion type field effect transistor (FET) and a Zener breakdown diode are employed to set a threshold level below which the control transistor remains latched and nonconducting to disconnect the supply voltage from the oscillator. The FET clamps the base and emitter electrodes of the control transistor together for latching the latter to hold it cut off when a coupled voltage is less than the prescribed value. During receipt of normal coupled ringing signals that are greater then the threshold, however, the FET opens to enable the control transistor which is then alternately driven into conduction and cutoff at the ringing frequency for providing pulses of supply voltage to power the carrier oscillator.
Inventors
- 👤 James A Steward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:23
CPC Classifications
H; H04; H04Q; H04Q5/00; H04Q5/24; H04Q5/245; H04M; H04M7/00; H04M7/16
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
365 words
A ringer guard circuit for use in a subscriber carrier telephone system for producing pulses of voltage in response to a central office ringing signal, comprising: a first resistor having first and second terminals; a source of reference voltage; first means for coupling the central office ringing signal to the first terminal of said first resistor; second means having a first input terminal connected to the second terminal of said first resistor, having a second input terminal connected to said reference voltage source, and having an output terminal, and being operative for selectively alternately operating in a first state to connect the reference voltage to the output terminal thereof and operating in a second state to disconnect the reference voltage from the output terminal thereof in response to opposite polarity halfcycles of ringing signals; a field effect transistor (FET) having one of its source and drain electrodes electrically connected to said voltage source, having the other one of its source and drain electrodes electrically connected to the second terminal of said first resistor, having a gate electrode, and having a range of threshold voltages between the gate electrode and the one of the source and drain electrodes that is connected to said voltage source over which said FET will change from operation in an on-state to operation in an off-state, said FET operating in the on-state for disabling said second means to disconnect the reference voltage from said second means output terminal when ringing signals are absent from the first terminal of said first resistor; third means associated with said FET gate electrode and the first terminal of said first resistor for effectively increasing the value of an input voltage to the latter for which said FET changes operating states; and, fourth means associated with said FET gate electrode and the one of said FET source and drain electrodes that is connected to said voltage source for selectively holding said FET in the off-state during application of a ringing signal to said first resistor for enabling said second means to alternately connect the output terminal thereof to and disconnect the output terminal thereof from the voltage source on opposite polarity half-cycles of the ringing signal.
Claim 2
Dependent Claim
365 words
A ringer guard circuit for use in a subscriber carrier telephone system for producing pulses of voltage in response to a central office ringing signal, comprising: a first resistor having first and second terminals; a source of reference voltage; first means for coupling the central office ringing signal to the first terminal of said first resistor; second means having a first input terminal connected to the second terminal of said first resistor, having a second input terminal connected to said reference voltage source, and having an output terminal, and being operative for selectively alternately operating in a first state to connect the reference voltage to the output terminal thereof and operating in a second state to disconnect the reference voltage from the output terminal thereof in response to opposite polarity halfcycles of ringing signals; a field effect transistor (FET) having one of its source and drain electrodes electrically connected to said voltage source, having the other one of its source and drain electrodes electrically connected to the second terminal of said first resistor, having a gate electrode, and having a range of threshold voltages between the gate electrode and the one of the source and drain electrodes that is connected to said voltage source over which said FET will change from operation in an on-state to operation in an off-state, said FET operating in the on-state for disabling said second means to disconnect the reference voltage from said second means output terminal when ringing signals are absent from the first terminal of said first resistor; third means associated with said FET gate electrode and the first terminal of said first resistor for effectively increasing the value of an input voltage to the latter for which said FET changes operating states; and, fourth means associated with said FET gate electrode and the one of said FET source and drain electrodes that is connected to said voltage source for selectively holding said FET in the off-state during application of a ringing signal to said first resistor for enabling said second means to alternately connect the output terminal thereof to and disconnect the output terminal thereof from the voltage source on opposite polarity half-cycles of the ringing signal.
Claim 3
Dependent Claim
36 words
The circuit according to claim 1 wherein said third means comprises a first diode which is a Zener diode that is electrically connected between the first terminal of said first resistor and said FET gate electrode.
Claim 4
Dependent Claim
52 words
The circuit according to claim 2 including a second diode in series with said first diode between the latter and the connection thereof to said FET gate electrode, said first and second diodes being connected back-to-back for selectively blocking current in one direction and passing a Zener current in the opposite direction.
Claim 5
Dependent Claim
38 words
The circuit according to claim 3 wherein said fourth means comprises a first capacitor electrically connected between said FET gate electrode and the one of said FET source and drain electrodes that is connected to said voltage source.
Claim 6
Dependent Claim
38 words
The circuit according to claim 4 wherein said second means comprises a bipolar transistor having base and emitter electrodes electrically connected across said FET drain and source electrodes, and having an output coupled from a collector electrode thereof.
Claim 7
Dependent Claim
51 words
The circuit according to claim 5 wherein said second means includes a third diode electrically connected across said bIpolar transistor base and emitter electrodes, said third diode conducting for half-cycles of ringing signal of only one polarity and said transistor conducting only for half-cycles of ringing signal of the opposite polarity.
Claim 8
Dependent Claim
21 words
The circuit according to claim 6 wherein said fourth means includes a second resistor connected in parallel with said first capacitor.
Claim 9
Dependent Claim
18 words
The circuit according to claim 7 including a second capacitor electrically connected across said bipolar transistor collector-base junction.
Claim 10
Dependent Claim
31 words
The circuit according to claim 8 including a fourth diode which is a Zener diode that is connected between the first terminal of said first resistor and a ground reference potential.
Claim 11
Dependent Claim
46 words
The circuit according to claim 9 wherein said first means comprises a resistive voltage divider for connection across central office tip and ring terminals, said divider having a tap thereon, the ringing voltage to the first terminal of said first resistor being coupled from said tap.
Claim 12
Dependent Claim
327 words
A ringer guard circuit operating in response to a central office ringing signal voltage, comprising: a first resistor having first and second terminals; a source of voltage; first means coupling the ringing voltage to the first terminal of said first resistor; a bipolar transistor having an emitter electrode electrically connected to said voltage source, having a base electrode electrically connected to the second terminal of said first resistor, and having a collector electrode; second means responsive to half-cycles of a ringing voltage of one polarity for effectively short circuiting said bipolar transistor base-emitter junction to cut off said bipolar transistor and responsive to half-cycles of a ringing voltage of the opposite polarity for effectively connecting an open circuit across said bipolar transistor base-emitter junction; a field effect transistor (FET) having drain, source, and gate electrodes, one of said drain and source electrodes being electrically connected to the second terminal of said first resistor, and the other one of said drain and source electrodes being electrically connected to said voltage source, said FET being on for holding said bipolar transistor cut off during the time interval that a ringing voltage is absent from the first terminal of said first resistor; third means associated with the first terminal of said first resistor and said FET gate electrode for passing current in one direction only for half-cycles of ringing voltage of one polarity that are greater than a prescribed threshold level for turning off said FET so as to enable said bipolar transistor and blocking current in the opposite direction; and, fourth means storing a signal voltage in response to operation of said third means in passing a current for maintaining said FET off during the duration of an applied ringing signal for enabling said bipolar transistor which is then alternately conducting and cut off on alternate half-cycles of the ringing voltage by operation of said second means for alternately connecting the source voltage to said bipolar transistor collector electrode.
Claim 13
Dependent Claim
327 words
A ringer guard circuit operating in response to a central office ringing signal voltage, comprising: a first resistor having first and second terminals; a source of voltage; first means coupling the ringing voltage to the first terminal of said first resistor; a bipolar transistor having an emitter electrode electrically connected to said voltage source, having a base electrode electrically connected to the second terminal of said first resistor, and having a collector electrode; second means responsive to half-cycles of a ringing voltage of one polarity for effectively short circuiting said bipolar transistor base-emitter junction to cut off said bipolar transistor and responsive to half-cycles of a ringing voltage of the opposite polarity for effectively connecting an open circuit across said bipolar transistor base-emitter junction; a field effect transistor (FET) having drain, source, and gate electrodes, one of said drain and source electrodes being electrically connected to the second terminal of said first resistor, and the other one of said drain and source electrodes being electrically connected to said voltage source, said FET being on for holding said bipolar transistor cut off during the time interval that a ringing voltage is absent from the first terminal of said first resistor; third means associated with the first terminal of said first resistor and said FET gate electrode for passing current in one direction only for half-cycles of ringing voltage of one polarity that are greater than a prescribed threshold level for turning off said FET so as to enable said bipolar transistor and blocking current in the opposite direction; and, fourth means storing a signal voltage in response to operation of said third means in passing a current for maintaining said FET off during the duration of an applied ringing signal for enabling said bipolar transistor which is then alternately conducting and cut off on alternate half-cycles of the ringing voltage by operation of said second means for alternately connecting the source voltage to said bipolar transistor collector electrode.
Claim 14
Dependent Claim
39 words
The circuit according to claim 11 wherein said third means comprises a first diode which is a Zener diode and a second-semiconductor diode electrically connected back-to-back between the first terminal of said first resistor and said FET gate electrode.
Claim 15
Dependent Claim
36 words
The circuit according to claim 12 wherein said fourth means comprises a first capacitor connected between said FET gate electrode and the one of said source and drain electrodes that is connected to said voltage source.
Claim 16
Dependent Claim
21 words
The circuit according to claim 13 wherein said fourth means includes a second resistor connected in parallel with said first capacitor.
Claim 17
Dependent Claim
14 words
The circuit according to claim 14 wherein said second means comprises a third-semiconductor diode.
Claim 18
Dependent Claim
20 words
The circuit according to claim 15 including a second capacitor electrically connected between said bipolar transistor cOllector and base electrodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-25 | 1979-02-24 | 1979-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-25 | 1983-02-24 | 1983-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-25 | 1987-02-24 | 1987-08-26 | $7700.00 | Window Closed / Lapsed |