US3898616A
Expired / Lapsed
US
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Threshold logic circuit for detecting exactly M out of a set of N signals
Assignee: AT&T Inc
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Filing: 1974-07-18
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Granted: 1975-08-05
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Expires: 1994-07-18
Abstract
Abstract Many of the complexities of prior art M-out-of-N detectors, including exhaustive gating and table look-up, are avoided in an M-out-of-N detector using threshold logic circuits suitable for integrated circuit fabrication. Input binary signals on each of N input leads direct an incremental current through one or the other of two summing resistors common to all inputs. One of the summing resistors sums current increments associated with the number of binary 1s in the N-bit input, and the other summing resistor derives the same result for Os. The differential voltage generated across the summing resistors is level shifted and combined with separately derived threshold signals before being applied to a pair of differential switches. The outputs from the circuit, typically wired-OR and wired-AND functions of the outputs of the differential switches, are the required detection signal and its complement. Other related applications of the input summing/differential switch combinations are also disclosed.
Inventors
- 👤 Charles Richmond Baugh
- 👤 Bruce Allen Wooley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:16
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/0813; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
84 words
Apparatus comprising A. input circuit means responsive to N input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > 1, and C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second difFerential signals exceeds a respective first predetermined value.
Claim 2
Dependent Claim
84 words
Apparatus comprising A. input circuit means responsive to N input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > 1, and C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second difFerential signals exceeds a respective first predetermined value.
Claim 3
Dependent Claim
135 words
Apparatus comprising A. input circuit means responsive to N input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > or = 1, wherein said level shifting means comprises means for generating N2 pairs of third differential signals, N2 > or = 1, C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second differential signal exceeds a respective first predetermined value, and D. N2 differential switches, each comprising means for generating an output whenever a respective one of said pairs of third differential signals fails to exceed a second predetermined value.
Claim 4
Dependent Claim
135 words
Apparatus comprising A. input circuit means responsive to N input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > or = 1, wherein said level shifting means comprises means for generating N2 pairs of third differential signals, N2 > or = 1, C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second differential signal exceeds a respective first predetermined value, and D. N2 differential switches, each comprising means for generating an output whenever a respective one of said pairs of third differential signals fails to exceed a second predetermined value.
Claim 5
Dependent Claim
112 words
Apparatus comprising A. input circuit means responsive to N binary-valued input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, said input circuit means comprising first summing means for generating first sum signals representing the number of input signals having one of said binary values, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > or = 1, and C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second differential signal exceeds a respective first predetermined value.
Claim 6
Dependent Claim
112 words
Apparatus comprising A. input circuit means responsive to N binary-valued input digital signals for generating a first differential pair of signals representative of the number of input signals having a prescribed value, said input circuit means comprising first summing means for generating first sum signals representing the number of input signals having one of said binary values, B. level shifting means responsive to said first differential pair of signals for generating N1 pairs of second differential signals, N1 > or = 1, and C. N1 first differential switches, each comprising means for generating an output whenever a respective one of said pairs of second differential signal exceeds a respective first predetermined value.
Claim 7
Dependent Claim
8 words
Apparatus according to claim 2 wherein N1 N2.
Claim 8
Dependent Claim
51 words
Apparatus according to claim 4 further comprising N1 combinational logic circuits, each responsive to the outputs of respective ones of said first and second differential switches for generating an output whenever a prescribed logic function is satisfied by said outputs of said respective ones of said first and second differential switches.
Claim 9
Dependent Claim
9 words
Apparatus according to claim 4 wherein N1 N2 1.
Claim 10
Dependent Claim
80 words
Apparatus according to claim 6 wherein said input signals are binary signals having a value of 0 or 1, and wherein said input circuit means comprises first summing means for generating first sum signals representing the number of input signals having a value of 0, second summing means for generating second sum signals representing the number of input signals having a value of 1, and said first differential pair of signals being represented by said first and second sum signals.
Claim 11
Dependent Claim
53 words
Apparatus according to claim 7 wherein said first and second summing means comprise, respectively, first and second summing resistors and first and second means responsive to applied input signals for applying to the respective one of said resistors an incremental current for each input signal having a value of 0 or 1, respectively.
Claim 12
Dependent Claim
59 words
Apparatus according to claim 5 wherein said first predetermined value is substantially equal to Mi-0.5, said second predetermined value is substantially equal to Mi+0.5, i 1,2, . . . ,N1, and wherein each of said first differential switches is uniquely paired with a second differential switch in providing said outputs to a respective one of said combinational logic circuits.
Claim 13
Dependent Claim
25 words
Apparatus according to claim 9 wherein said combinational logic circuits comprise an AND circuit and an OR circuit for each of said paired differential switches.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-08-04 | 1979-02-03 | 1979-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-08-04 | 1983-02-03 | 1983-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-08-04 | 1987-02-03 | 1987-08-05 | $7700.00 | Window Closed / Lapsed |