Process for fabricating schottky barrier phototransistor

Claim 2

IN A PROCESS FOR FABRICATING A PHOTOTRANSISTOR, THE STEPS COMPRISING: DIFFUSING A P-TYPE IMPURITY INTO A PREDETERMINED AREA OF A SUBSTRATE OF III-V COMPOUND SEMICONDUCTOR MATERIAL OF N-TYPE TO FORM A P-TYPE REGION IN SAID N-TYPE SUBSTRATE SUCH THAT A PHOTOSENSITIVE DIODE JUNCTION IS PROVIDED BETWEEN THE P-TYPE REGION AND THE N-TYPE SUBSTRATE, REMOVING AT LEAST A PORTION OF THE SUBSTRATE IN SAID PREDETERMINED AREA COMPRISING THE P-TYPE REGION TO REMOVE SURFACE OXIDES THEREFROM AND TO REDUCE THE LEVEL OF P-TYPE IMPURITY CONCENTRATION BY EXPOSING THE P-TYPE RGION AT A DEPTH HAVING, A SUFFICIENTLY LOW IMPURITY CONCENTRATION FOR SUBSEQUENT FORMATION OF A RECTIFYING CONTACT WITH A METAL FILM TO BE DEPOSITED THEREON, AND DEPOSITING A METAL FILM ON SAID EXPOSED PORTION OF SAID P-TYPE REGION TO PRODUCE A RECTIFYING JUNCTION THEREWITH.

Claim 3

A process as set forth in claim 1, wherein the removal of at least a portion of the substrate in said predetermined area comprising the p-type region is accomplished by etching.

Claim 4

A process as set forth in claim 1, further including placing the substrate after deposit of said metal film on said exposed portion of said p-type region in a reducing atmosphere to reduce any oxide formed at the junction between said metal film and said p-type region.

Claim 5

The process defined in claim 1 wherein the p-type impurity is diffused from the vapor stage using a two zone process to produce an error function diffusion profile.

Claim 6

A process as set forth in claim 1, wherein the substrate of III-V compound semiconductor material of n-type is selected from the group consisting of indium arsenide, indium antimonide and gallium antimonide.

Claim 7

A process as set forth in claim 5, wherein said substrate is n-type indium arsenide.

Claim 8

A process as set forth in claim 5, wherein said p-type impurity diffused into said predetermined area of said substrate is selected from the group consisting of cadmium, zinc and magnesium.

Claim 9

A process as set forth in claim 7, wherein said p-type impurity is cadmium.

Claim 10

A process for fabricating a phototransistor comprising the steps of: selectively diffusing a p-type impurity into a predetermined area of an n-type substrate of III-V compound semiconductor material to form a p-type region in said n-type substrate such that a photosensitive diode junction is provided between said p-type region and said n-type substrate, removing at least a portion of said substrate in said predetermined area comprising the p-type region to remove surface oxides therefrom and to reduce the level of p-type impurity concentration by exposing the p-type region at a depth having a sufficiently low impurity concentration enabling said p-type region to be capable of producing a rectifying junction with a metal film to be deposited thereon, and depositing a patterned metal film on said exposed portion of said p-type region and on the surface of said n-type substrate at a position spaced from said p-type region so as to simultAneously produce a rectifying junction between said exposed portion of the p-type region and said metal film and an ohmic contact between said substrate surface and said metal film at the position spaced from said p-type region.

Claim 11

A process for fabricating a phototransistor comprising the steps of: selectively diffusing a p-type impurity into a predetermined area of an n-type substrate of III-V compound semiconductor material to form a p-type region in said n-type substrate such that a photosensitive diode junction is provided between said p-type region and said n-type substrate, removing at least a portion of said substrate in said predetermined area comprising the p-type region to remove surface oxides therefrom and to reduce the level of p-type impurity concentration by exposing the p-type region at a depth having a sufficiently low impurity concentration enabling said p-type region to be capable of producing a rectifying junction with a metal film to be deposited thereon, and depositing a patterned metal film on said exposed portion of said p-type region and on the surface of said n-type substrate at a position spaced from said p-type region so as to simultAneously produce a rectifying junction between said exposed portion of the p-type region and said metal film and an ohmic contact between said substrate surface and said metal film at the position spaced from said p-type region.

Claim 12

A process as set forth in claim 9, wherein the removal of at least a portion of the substrate in said predetermined area comprising the p-type region is accomplished by etching.

Claim 13

A process for fabricating a phototransistor comprising the steps of: providing a substrate of n-type indium arsenide material, placing said substrate and a p-type impurity consisting of cadmium into an evacuated chamber, heating said substrate to a first temperature and said cadmium to a second temperature lower than said first temperature within said evacuated chamber to diffuse said cadmium into a predetermined area of said substrate to form a p-type region therein such that a photosensitive diode junction is provided between the p-type region and said substrate having an error function diffusion profile, removing at least a portion of said substrate in said predetermined area comprising said p-type region to remove surface oxides therefrom and to reduce the level of p-type impurity concentration by exposing the p-type region at a depth having a sufficiently low impurity concentration within said error function diffusion profile to enable said p-type region to produce a rectifying junction with a metal film to be deposited thereon, and depositing a metal film on said exposed portion of the p-type region to produce a rectifying junction.

Claim 14

A process for fabricating a phototransistor comprising the steps of: providing a substrate of n-type indium arsenide material, placing said substrate and a p-type impurity consisting of cadmium into an evacuated chamber, heating said substrate to a first temperature and said cadmium to a second temperature lower than said first temperature within said evacuated chamber to diffuse said cadmium into a predetermined area of said substrate to form a p-type region therein such that a photosensitive diode junction is provided between the p-type region and said substrate having an error function diffusion profile, removing at least a portion of said substrate in said predetermined area comprising said p-type region to remove surface oxides therefrom and to reduce the level of p-type impurity concentration by exposing the p-type region at a depth having a sufficiently low impurity concentration within said error function diffusion profile to enable said p-type region to produce a rectifying junction with a metal film to be deposited thereon, and depositing a metal film on said exposed portion of the p-type region to produce a rectifying junction.

Claim 15

A process as set forth in claim 11, wherein said metal film is simultaneously deposited on said exposed portion of said p-type region and on the surface of said substrate at a position spaced from said p-type region to produce said rectifying junction between said exposed portion of said p-type region and said metal film and an ohmic contact between said substrate surface and said metal film at the position spaced from said p-type region.

Claim 16

A process as set forth in claim 11, wherein said portion of said substrate in said predetermined area comprising said p-type region is removed until the final thickness of said p-type region is approximately 10 microns.

Claim 17

A process as set forth in claim 11, wherein said substrate and said cadmium are subjected to heating at said first and second temperatures respectively until said p-type region has a surface concentration of about 8 X 1016 atoms per cubic centimeter.

Claim 18

A process as set forth in claim 11, wherein said metal film is deposited on said exposed portion of said p-type region to a thickness of approximately 5,000 angstroms.

Claim 19

A process as set forth in claim 11, wherein said substrate is heated to a first temperature of approximately 650*C and said cadmium is heated to a second temperature of approximately 600*C.