US3896341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protecting device for a semiconductor memory apparatus
Assignee: Toshiba Corp
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Filing: 1973-04-20
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Granted: 1975-07-22
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Expires: 1993-04-20
Abstract
Abstract A protecting device for a semiconductor memory which protects the plural semiconductor memory elements from damage due to an abnormal pulse being received from the driving circuits. The output signals from the precharge and chip select signal drivers in a MOS-RAM are sampled and time-delayed. The sampled signals are compared with the time delayed signals in gating circuits. If the sampled signals exceed a predetermined pulse width, sensing means are actuated to activate the alarm and terminate the source voltage to prevent damage to the memory elements.
Inventors
- 👤 Koji Kodama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:28
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/50; G; G06; G06F; G06F11/00; G06F11/002; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
265 words
Apparatus for protecting the semi-conductor memory elements in a semiconductor device from damage due to abnormal pulses from the driving circuitry thereof, which comprises: means for sampling a pulse signal from said driving circuitry; means for time-delaying said pulse signal; means for comparing said pulse signal with said time-delayed pulse signal and for issuing an output signal indicative of whether said pulse signal exceeds a pre-determined pulse width; said time-delaying and comparing means comprising a first inverter having an input and an output for receiving as its input the pulse signal from said driving circuitry; a second inverter having an input and an output; a first delay circuit having an input and an output; a second delay circuit having an input and an output; a first NAND gate having two inputs and an output; a second NAND gate having two inputs and an output; means connecting the output of the first inverter to the input of the first delay circuit and to an input of the first NAND gate; means connecting the output of the first delay circuit to the other input of the first NAND gate; means connecting the output of the first NAND gate to the input of the second inverter; means connecting the output of the second inverter to the input of the second delay circuit and to an input of the second NAND gate; means connecting the output of the second delay circuit to the other input of the second NAND gate; the output of the second NAND gate being indicative of whether said pulse signal exceeds a predetermined pulse width.
Claim 2
Dependent Claim
265 words
Apparatus for protecting the semi-conductor memory elements in a semiconductor device from damage due to abnormal pulses from the driving circuitry thereof, which comprises: means for sampling a pulse signal from said driving circuitry; means for time-delaying said pulse signal; means for comparing said pulse signal with said time-delayed pulse signal and for issuing an output signal indicative of whether said pulse signal exceeds a pre-determined pulse width; said time-delaying and comparing means comprising a first inverter having an input and an output for receiving as its input the pulse signal from said driving circuitry; a second inverter having an input and an output; a first delay circuit having an input and an output; a second delay circuit having an input and an output; a first NAND gate having two inputs and an output; a second NAND gate having two inputs and an output; means connecting the output of the first inverter to the input of the first delay circuit and to an input of the first NAND gate; means connecting the output of the first delay circuit to the other input of the first NAND gate; means connecting the output of the first NAND gate to the input of the second inverter; means connecting the output of the second inverter to the input of the second delay circuit and to an input of the second NAND gate; means connecting the output of the second delay circuit to the other input of the second NAND gate; the output of the second NAND gate being indicative of whether said pulse signal exceeds a predetermined pulse width.
Claim 3
Dependent Claim
226 words
Apparatus for protecting the semiconductor memory elements in a semiconductor memory device from damage due to abnormal pulses from a precharge signal driver and/or a chip select signal driver, which comprises: first and second diode means for sampling a pulse signal from said precharge signal driver and said chip select signal driver, respectively; first and second means connected to receive the output signals from said first and second sampling means, respectively, for establishing respective voltage signals indicative of the presence or absence of said output signals; first and second wave-adjusting means connected to receive said voltage signals from said first and second establishing means, respectively, said first and second wave-adjusting means including means for time-delaying said voltage signals, gating means for comparing said voltage signals with said time delayed voltage signals and for issuing first and second difference signals indicative of whether said voltage signals exceed a predetermined pulse width, means for time-delaying said first and second difference signals, gating means for comparing said first and second difference signals with said time-delayed first and second difference signals and for issuing third and fourth difference signals indicative of whether said first and second difference signals exceed a predetermined pulse width; and sensing means for receiving as its inputs the outputs of said first and second wave-adjusting means and for issuing an output signal responsive to said inputs.
Claim 4
Dependent Claim
226 words
Apparatus for protecting the semiconductor memory elements in a semiconductor memory device from damage due to abnormal pulses from a precharge signal driver and/or a chip select signal driver, which comprises: first and second diode means for sampling a pulse signal from said precharge signal driver and said chip select signal driver, respectively; first and second means connected to receive the output signals from said first and second sampling means, respectively, for establishing respective voltage signals indicative of the presence or absence of said output signals; first and second wave-adjusting means connected to receive said voltage signals from said first and second establishing means, respectively, said first and second wave-adjusting means including means for time-delaying said voltage signals, gating means for comparing said voltage signals with said time delayed voltage signals and for issuing first and second difference signals indicative of whether said voltage signals exceed a predetermined pulse width, means for time-delaying said first and second difference signals, gating means for comparing said first and second difference signals with said time-delayed first and second difference signals and for issuing third and fourth difference signals indicative of whether said first and second difference signals exceed a predetermined pulse width; and sensing means for receiving as its inputs the outputs of said first and second wave-adjusting means and for issuing an output signal responsive to said inputs.
Claim 5
Dependent Claim
28 words
The apparatus according to claim 2 wherein said sensing means comprises a NAND gate, the output of which is connected to alarm means and source voltage cut-off means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-21 | 1979-01-20 | 1979-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-21 | 1983-01-20 | 1983-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-21 | 1987-01-20 | 1987-07-22 | $7700.00 | Window Closed / Lapsed |