US3895237A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Peak detector
Assignee: International Business Machines Corp
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Filing: 1973-07-05
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Granted: 1975-07-15
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Expires: 1993-07-05
Abstract
Abstract A peak detector generates a signal representing the occurrence of a peak in an input signal waveform each time the slope of the input signal waveform reverses and travels through a dead zone defined by the difference between two different reference voltages. The dead zone which prevents short term reversals in the input signal waveform due to noise and other aberrations from generating signals representing valid peaks and which is defined by the difference between the two reference voltages is easily adjusted such as by varying the value of a single resistor in one embodiment to adapt the peak detector circuit to different input signal waveform situations. A common terminal which is coupled to the two different reference voltages through opposite voltageresponsive devices has a voltage which varies directly in response to the input signal waveform as applied thereto by a voltage coupling device such as a capacitor. The voltageresponsive devices maintain the voltage of the common junction within the range defined by the two different reference voltages by conducting whenever the common junction voltage equals either of the reference voltages. Alternate conductions of the voltageresponsive devices are used to trigger a bistable device which provides an accurate representation of the peaks of the input signal waveform.
Inventors
- 👤 Jerome Danforth Harr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:52
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/10009; H; H03; H03K; H03K5/00; H03K5/153; H03K5/1532
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
280 words
A circuit for detecting peaks of an input signal waveform comprising: means defining two different signal levels; common junction means having a signal thereat; means coupled to the common junction means and responsive to the input waveform for varying the level of the signal at the junction means between the two different signal levels in direct relation with the input signal waveform, the level of the signal at the junction means being varied in response to each reversal in the slope of the input waveform; first means coupled to the common junction means and responsive to one of the two different signal levels for generating a first peak signal when the level of the signal at the junction means is substantially equal to said one of the two different signal levels, said first means including means for conducting whenever the level of the signal at the junction means substantially equals said one of the two different levels to maintain the level of the signal at the junction means substantially equal to said one of the two different signal levels; and second means coupled to the common junction means and responsive to the other one of the two different signal levels for generating a second peak signal when the level of the signal at the junction means is substantially equal to said other one of the two different signal levels, said second means including means for conducting whenever the level of the signal at the junction means substantially equals said other one of the two different signal levels to maintain the level of the signal at the junction means substantially equal to said other one of the two different signal levels.
Claim 2
Dependent Claim
280 words
A circuit for detecting peaks of an input signal waveform comprising: means defining two different signal levels; common junction means having a signal thereat; means coupled to the common junction means and responsive to the input waveform for varying the level of the signal at the junction means between the two different signal levels in direct relation with the input signal waveform, the level of the signal at the junction means being varied in response to each reversal in the slope of the input waveform; first means coupled to the common junction means and responsive to one of the two different signal levels for generating a first peak signal when the level of the signal at the junction means is substantially equal to said one of the two different signal levels, said first means including means for conducting whenever the level of the signal at the junction means substantially equals said one of the two different levels to maintain the level of the signal at the junction means substantially equal to said one of the two different signal levels; and second means coupled to the common junction means and responsive to the other one of the two different signal levels for generating a second peak signal when the level of the signal at the junction means is substantially equal to said other one of the two different signal levels, said second means including means for conducting whenever the level of the signal at the junction means substantially equals said other one of the two different signal levels to maintain the level of the signal at the junction means substantially equal to said other one of the two different signal levels.
Claim 3
Dependent Claim
40 words
A circuit in accordance with claim 1, further including bistable means for assuming a first state in response to generation of the first peak signal and for assuming a second state in response to generation of the second peak signal.
Claim 4
Dependent Claim
176 words
A circuit for detecting peaks of an input voltage waveform comprising: means defining first and second voltages of different value; means responsive to the first and second voltages and including a terminal having a voltage thereat for maintaining the terminal voltage within the range defined by the first and second voltages; means coupled to the terminal and responsive to the input voltage waveform for increasing the terminal voltage in response to iNcreases in the input voltage waveform and for decreasing the terminal voltage in response to decreases in the input voltage waveform; means responsive to the first and second voltages and the terminal voltage for generating a peak signal whenever the terminal voltage substantially equals either of the first and second voltages; a bistable circuit; and an electrical network connecting the bistable circuit to the means for generating a peak signal, the electrical network being operative to generate a bilevel signal at the output of the bistable circuit which changes between a first level and a second level in response to generation of the peak signals.
Claim 5
Dependent Claim
176 words
A circuit for detecting peaks of an input voltage waveform comprising: means defining first and second voltages of different value; means responsive to the first and second voltages and including a terminal having a voltage thereat for maintaining the terminal voltage within the range defined by the first and second voltages; means coupled to the terminal and responsive to the input voltage waveform for increasing the terminal voltage in response to iNcreases in the input voltage waveform and for decreasing the terminal voltage in response to decreases in the input voltage waveform; means responsive to the first and second voltages and the terminal voltage for generating a peak signal whenever the terminal voltage substantially equals either of the first and second voltages; a bistable circuit; and an electrical network connecting the bistable circuit to the means for generating a peak signal, the electrical network being operative to generate a bilevel signal at the output of the bistable circuit which changes between a first level and a second level in response to generation of the peak signals.
Claim 6
Dependent Claim
67 words
A circuit in accordance with claim 3, wherein the means for maintaining the terminal voltage within the range defined by the first and second voltages comprises a first device coupled to the terminal and operative to conduct current whenever the terminal voltage equals the first voltage and a second device coupled to the terminal and operative to conduct current whenever the terminal voltage equals the second voltage.
Claim 7
Dependent Claim
37 words
A circuit in accordance with claim 4, wherein each of the first and second devices includes a unilateral conducting device coupled to be biased into conduction whenever the terminal voltage equals the first or the second voltage.
Claim 8
Dependent Claim
143 words
A circuit for detecting peaks of an input signal waveform comprising: a first reference terminal having a fixed high reference voltage thereat; a second reference terminal having a fixed low reference voltage thereat; a common terminal; a first diode coupled between the common terminal and the first reference terminal and poled to pass current in a direction from the common terminal to the first reference terminal; a second diode coupled between the common terminal and the second reference terminal and poled to pass current in a direction from the second reference terminal to the common terminal; an input terminal coupled to receive the input signal waveform; a capacitor coupled between the input terminal and the common terminal; and a bistable circuit coupled to be set by current flow in the first diode and to be reset by current flow in the second diode.
Claim 9
Dependent Claim
143 words
A circuit for detecting peaks of an input signal waveform comprising: a first reference terminal having a fixed high reference voltage thereat; a second reference terminal having a fixed low reference voltage thereat; a common terminal; a first diode coupled between the common terminal and the first reference terminal and poled to pass current in a direction from the common terminal to the first reference terminal; a second diode coupled between the common terminal and the second reference terminal and poled to pass current in a direction from the second reference terminal to the common terminal; an input terminal coupled to receive the input signal waveform; a capacitor coupled between the input terminal and the common terminal; and a bistable circuit coupled to be set by current flow in the first diode and to be reset by current flow in the second diode.
Claim 10
Dependent Claim
53 words
A circuit in accordance with claim 6, wherein the first and second diodes are light emitting diodes, and further including first phototransistor means responsive to light emitted by the first diode for setting the bistable circuit and second phototransistor means responsive to light emitted by the second diode for resetting the bistable circuit.
Claim 11
Dependent Claim
155 words
A circuit for detecting peaks of an input signal waveform comprising: a first reference terminal having a fixed first reference voltage thereat; a second reference terminal having a fixed second reference voltage thereat; a first operational amplifier having first and second input terminals and an output terminal, the first input terminal being coupled to the first reference terminal; a second operational amplifier having first and second input terminals and an output terminal, the first input terminal being coupled to the second reference terminal; a first unilateral current conducting device coupled between the second input terminal and the output terminal of the first operational amplifier; a second unilateral current conducting device coupled between the second input terminal and the output terminal of the second operational amplifier; and capacitor means having one end coupled to the second input terminals of the first and second operational amplifiers and an opposite end coupled to receive the input signal waveform.
Claim 12
Dependent Claim
155 words
A circuit for detecting peaks of an input signal waveform comprising: a first reference terminal having a fixed first reference voltage thereat; a second reference terminal having a fixed second reference voltage thereat; a first operational amplifier having first and second input terminals and an output terminal, the first input terminal being coupled to the first reference terminal; a second operational amplifier having first and second input terminals and an output terminal, the first input terminal being coupled to the second reference terminal; a first unilateral current conducting device coupled between the second input terminal and the output terminal of the first operational amplifier; a second unilateral current conducting device coupled between the second input terminal and the output terminal of the second operational amplifier; and capacitor means having one end coupled to the second input terminals of the first and second operational amplifiers and an opposite end coupled to receive the input signal waveform.
Claim 13
Dependent Claim
16 words
A circuit in accordance with claim 8, wherein each unilaterial current conducting device comprises a diode.
Claim 14
Dependent Claim
17 words
A circuit in accordance with claim 8, wherein each unilateral conducting device comprises at least one transistor.
Claim 15
Dependent Claim
100 words
A circuit in accordance with claim 10, wherein each unilateral conducting device comprises a first transistor coupled to be biased into conduction whenever the voltage at the second input terminal of the associated operational amplifier is substantially equal to the reference voltage at the first input terminal of the operational amplifier, a plurality of transistors coupled to clamp the second input terminal at a voltage substantially equal to the reference voltage at the first input terminal of the operational amplifier whenever the first transistor conducts, and a second transistor coupled to provide an output signal whenever the first transistor conducts.
Claim 16
Dependent Claim
32 words
A circuit in accordance with claim 8, further including a bistable circuit coupled to be set and reset by signals at the output terminals of the first and second operational amplifiers respectively.
Claim 17
Dependent Claim
65 words
A circuit in accordance with claim 12, further including at least one trigger pulse generating circuit coupled between the output terminal of one of the operational amplifiers and one of the input terminals of the bistable circuit, the trigger pulse generating circuit being operative to generate a pulse in response to a signal change of given sense at the output terminal of the operational amplifier.
Claim 18
Dependent Claim
76 words
A circuit in accordance with claim 12, further including at least one trigger signal generating circuit coupled between the output terminal of one of the operational amplifiers and one of the input terminals of the bistable circuit, the trigger signal generating circuit being operative to generate a bilevel signal which changes from a first level to a second level in response to a signal change of given sense at the output terminal of the operational amplifier.
Claim 19
Dependent Claim
66 words
A circuit in accordance with claim 8, further including a bistable circuit having an input circuit coupled to the output terminals of said first and second operational amplifiers and having at least one output terminal, said bistable circuit being operative to provide two different signal levels at said output terminal in response to signals at the output terminals of the first and second operational amplifiers respectively.
Claim 20
Dependent Claim
70 words
A circuit in accordance with claim 12, further including an electrical network connecting said bistable circuit to said output terminals of said first and second operational amplifiers, said electrical network being operative to generate a bilevel signal at the output of said bistable circuit which changes between a first level and a second level in response to signal changes of given sense at the output terminals of the operational amplifiers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-07-14 | 1979-01-13 | 1979-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-07-14 | 1983-01-13 | 1983-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-07-14 | 1987-01-13 | 1987-07-15 | $7700.00 | Window Closed / Lapsed |