US3893171A
Expired / Lapsed
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Signal adjustment circuit
Assignee: International Business Machines Corp
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Filing: 1974-03-25
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Granted: 1975-07-01
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Expires: 1994-03-25
Abstract
Abstract Signals read back from a magnetic record medium have assigned sets of legal wavelengths, i.e., elapsed times between any successive two transitions. During readback, the zero crossover, hence the transition location, can be unintentionally phase shifted (as by base line changes) by the channel. The signal is detected and converted to a string of 1''s and 0''s, wherein the 1''s represent detected transitions. A set of three such wavelengths is analyzed for illegal code values representing illegal wavelengths. The illegal code value is then converted to a legal code in accordance with the two adjacent code values in such set. In one embodiment, the illegal code value represented a wavelength that was too short. One of the transitions defining the illegal wavelength is shifted in time toward the longer of two other wavelengths immediately abutting the short illegal wavelength.
Inventors
- 👤 John W Marshall
- 👤 Jr Earl G Mcdonal
- 👤 Phillip B Roath
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:59
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
112 words
A transition adjustment method, including the following steps in combination: detecting an incoming signal and generating a string of timed 1 and 0 indicating digital signals having a series of transitions and representative of said incoming signal zero crossovers; analyzing first, second, and third successive wavelengths separated by a given two signal transitions; determining which of said first and third wavelengths are longer; and either adjusting a first one of said two signal transitions in time to make said second wavelength longer when said first wavelength being longer than said third wavelength or adjusting a second one of said two signal transitions when said third wavelength is longer than said first wavelength.
Claim 2
Dependent Claim
112 words
A transition adjustment method, including the following steps in combination: detecting an incoming signal and generating a string of timed 1 and 0 indicating digital signals having a series of transitions and representative of said incoming signal zero crossovers; analyzing first, second, and third successive wavelengths separated by a given two signal transitions; determining which of said first and third wavelengths are longer; and either adjusting a first one of said two signal transitions in time to make said second wavelength longer when said first wavelength being longer than said third wavelength or adjusting a second one of said two signal transitions when said third wavelength is longer than said first wavelength.
Claim 3
Dependent Claim
55 words
The method set forth in claim 1 further including the steps of: reading a signal from a magnetic record member to generate said incoming signal; determining whether or not said second wavelength is too short, and if too short, adjusting said first or second transition toward a longer one of said first and third wavelengths.
Claim 4
Dependent Claim
144 words
A digital signal transition adjustment circuit including in combination: a shift register having a predetermined number of stages interconnected to shift data signals in a first direction from an input stage toward an output stage, each stage for containing a digital data signal; decoding means connected to certain stages of said shift register for detecting the signal contents thereof including AND circuit means responsive to a giveN plurality of said stages central of said shift register for actuating a transition adjustment; and second AND circuit means responsive to said decoding means and to said first-mentioned AND circuit means in accordance with signal content of said central stages for supplying a reset signal to a given one of said stages and supplying a set signal to another one of said stages for adjusting signal contents thereof in accordance with the permutation in said shift register.
Claim 5
Dependent Claim
144 words
A digital signal transition adjustment circuit including in combination: a shift register having a predetermined number of stages interconnected to shift data signals in a first direction from an input stage toward an output stage, each stage for containing a digital data signal; decoding means connected to certain stages of said shift register for detecting the signal contents thereof including AND circuit means responsive to a giveN plurality of said stages central of said shift register for actuating a transition adjustment; and second AND circuit means responsive to said decoding means and to said first-mentioned AND circuit means in accordance with signal content of said central stages for supplying a reset signal to a given one of said stages and supplying a set signal to another one of said stages for adjusting signal contents thereof in accordance with the permutation in said shift register.
Claim 6
Dependent Claim
131 words
The circuit set forth in claim 3 wherein said central stages consist of two stages and said first-mentioned AND circuit means being responsive to two binary 1 indicating signals in said two stages for actuating said transition adjustment, and said second AND circuit means having a first AND portion for supplying said reset signal to one of said central stages and said set signal to another one of said central stages, and said second AND circuit means having a second AND portion for supplying a reset signal to predetermined ones of said shift register stages adjacent said central stages and intermediate said output stage and said central stages and a preset signal to another one of said shift register stages intermediate said output stage and said predetermined one shift register stage.
Claim 7
Dependent Claim
55 words
The apparatus set forth in claim 4 further including clocking means for supplying shift signals to said shift register shifting said data signal through said shift register in a synchronous manner and said clocking means supplying control signals intermediate said shift signals to said second AND circuit means for timing said set and reset signals.
Claim 8
Dependent Claim
89 words
The apparatus set forth in claim 5 wherein said decoding means actuates said first-mentioned signal transition adjustment when there is initially a greater plurality of successive 0 data signals in said shift register stages intermediate said output stage and said central stages than in stages intermediate said input stage and said central stages and actuating said second-mentioned signal transition adjustment when there is a greater number of successive 0''s in the stages intermediate said input stage and said central stages than intermediate said output stage and said central stages.
Claim 9
Dependent Claim
206 words
A signal adjustment circuit for correcting transposition errors comprising a shift register having N stages, N being a positive integer greater than 4; clock means for synchronously and continuously shifting data signals through said shift register from an input stage 1 toward an output stage N, through successive shift register stages 2, 3, ..., said data signal respresenting 1''s and 0''s; means responsive to a pair of 1 signals in N/2 and in an (N/2) + 1 shift register stage to initiate changes in signal states in a selected two of said shift register stages; decoding means responsive to a greater number of 0''s in said shift register stages between (N/2) + 1 and N than in said shift register stages 0 through (N/2) - 1 to clear a signal state from 1 to 0 in said (N/2) + 2 shift register stage and to preset said (N/2) + 3 shift register stage; and further means responsive to a greater number of 0''s being in said shift register stages 0 through (N/2) - 1 than in said stages (N/2) + 2 through N to supply a preset signal to said N/2 shift register stage and a reset signal to said (N/2) + 1 shift register stage.
Claim 10
Dependent Claim
206 words
A signal adjustment circuit for correcting transposition errors comprising a shift register having N stages, N being a positive integer greater than 4; clock means for synchronously and continuously shifting data signals through said shift register from an input stage 1 toward an output stage N, through successive shift register stages 2, 3, ..., said data signal respresenting 1''s and 0''s; means responsive to a pair of 1 signals in N/2 and in an (N/2) + 1 shift register stage to initiate changes in signal states in a selected two of said shift register stages; decoding means responsive to a greater number of 0''s in said shift register stages between (N/2) + 1 and N than in said shift register stages 0 through (N/2) - 1 to clear a signal state from 1 to 0 in said (N/2) + 2 shift register stage and to preset said (N/2) + 3 shift register stage; and further means responsive to a greater number of 0''s being in said shift register stages 0 through (N/2) - 1 than in said stages (N/2) + 2 through N to supply a preset signal to said N/2 shift register stage and a reset signal to said (N/2) + 1 shift register stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |