Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
339 words
A coincidence measuring circuit for indicating the time interval between the pulses of two separate periodic pulse trains i1 and i2 having dissimilar frequencies F1 and F2, comprising a first bistable multivibrator triggerable to a first stable state in response to a pulse on a first input thereof and triggerable to a second stable state in response to a pulse on a second input thereof for providing an output signal level on a first output thereof in response to the first stable state and for providing an output level on a second output thereof in response to the second stable state, means connecting the pulse train i1 to the first input of the first bistable multivibrator, means connecting the pulse train i2 to the second input of the first bistable multivibrator, timing means connected to the first output of the first bistable multivibrator for providing a timing output pulse a predetermined delay interval after the initiation of the output signal level on the first output of the first bistable multivibrator, a second bistable multivibrator triggerable to a first stable state in response to a pulse on a first input thereof and triggerable to a second stable state in response to a pulse on a second input thereof for providing an output level on a first output thereof in response to the first stable state and for providing an output level on a second output thereof in response to the second stable state, means connecting the pulse train i1 and to the first input of the second bistable multivibrator, means connecting the output of the timing means to the second input of the second bistable multivibrator, and a coincidence gate having inputs connected to the second output of the first bistable multivibrator and to the first output of the second bistable multivibrator for providing a coincidence output signal indicating that the period between a pulse of the pulse train i1 and the next following pulse of the pulse train i2 was less than the delay interval of the timing means.
Claim 2
Dependent Claim
339 words
A coincidence measuring circuit for indicating the time interval between the pulses of two separate periodic pulse trains i1 and i2 having dissimilar frequencies F1 and F2, comprising a first bistable multivibrator triggerable to a first stable state in response to a pulse on a first input thereof and triggerable to a second stable state in response to a pulse on a second input thereof for providing an output signal level on a first output thereof in response to the first stable state and for providing an output level on a second output thereof in response to the second stable state, means connecting the pulse train i1 to the first input of the first bistable multivibrator, means connecting the pulse train i2 to the second input of the first bistable multivibrator, timing means connected to the first output of the first bistable multivibrator for providing a timing output pulse a predetermined delay interval after the initiation of the output signal level on the first output of the first bistable multivibrator, a second bistable multivibrator triggerable to a first stable state in response to a pulse on a first input thereof and triggerable to a second stable state in response to a pulse on a second input thereof for providing an output level on a first output thereof in response to the first stable state and for providing an output level on a second output thereof in response to the second stable state, means connecting the pulse train i1 and to the first input of the second bistable multivibrator, means connecting the output of the timing means to the second input of the second bistable multivibrator, and a coincidence gate having inputs connected to the second output of the first bistable multivibrator and to the first output of the second bistable multivibrator for providing a coincidence output signal indicating that the period between a pulse of the pulse train i1 and the next following pulse of the pulse train i2 was less than the delay interval of the timing means.
Claim 3
Dependent Claim
30 words
A coincidence measuring circuit as claimed in claim 1, wherein the delay interval of the timing means has a value equal to the absolute value of 1/f1 - 1/f2 seconds.
Claim 4
Dependent Claim
112 words
A coincidence measuring circuit as claimed in claim 1, wherein the timing means comprises a frequency generator means for providing counting pulses at a frequency higher than f1 and f2, a binary pulse counter, an AND-gate having an input connected to the output of the frequency generator means and a further input connected to the first output of the first bistable multivibrator for passing the counting pulses to the binary pulse counter in response to the first stable state of the first bistable multivibrator, the counter providing the delayed pulse to the second input of the second bistable multivibrator in response to a predetermined number of counting pulses from the frequency generator.
Claim 5
Dependent Claim
27 words
A coincidence measuring circuit as claimed in claim 3 further comprising means operating in response to the coincidence output signal for storing the number in the counter.