US3892952A
Expired / Lapsed
US
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Digital differentiation circuit
Assignee: Denso Corp
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Filing: 1974-03-20
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Granted: 1975-07-01
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Expires: 1994-03-20
Abstract
Abstract The present invention provides a digital differentiation circuit comprising a reference pulse generating circuit for generating reference pulses having a predetermined frequency, a speed detector for generating output pulses having a frequency proportional to a vehicle speed to be measured, and a timing pulse generating circuit for generating reference timing pulses, wherein the leading edge of the detector output pulse and the leading edge of the reference timing pulse are synchronized with the reference pulse, and the trailing edge of the reference timing pulse is extended to the leading edge of the first detector output pulse appearing after the end of the duration of the reference timing pulse to determine a counting period, whereby the number of the detector output pulses and the number of the reference pulses received during this extended counting period are respectively counted by a first and second counters, and the counts of the first and second counters are subjected to the operation of division to obtain a speed which is subjected to the operation of subtraction with the previously obtained speed.
Inventors
- 👤 Akira Shibata
- 👤 Atutoshi Okamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:51
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/62; B; B60; B60T; B60T8/00; B60T8/17; B60T8/172; G01; G01P; G01P15/00; G01P15/16
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
315 words
A digital differentiation circuit for differentiating a frequency proportional to a detected displacement speed, comprising: a reference pulse generating circuit for generating reference pulses having a predetermined frequency; a displacement speed detector for generating output pulses having a frequency proportional to a detected displacement speed; a timing pulse generating circuit for recurrently generating a reference timing pulse having a predetermined reference time width; a synchronization circuit connected to said timing pulse generating circuit, said reference pulse generating circuit and said displacement speed detector whereby the leading edge of said reference timing pulse is synchronized with the leading edge of said detector output pulse and the leading edge of said reference pulse to continuously generate said reference pulse and said detector output pulse synchronized with each other during a counting period extending from the leading edge of said synchronized reference timing pulse to the trailing edge thereof which was extended to the first leading edge of said detector output pulse generated after the termination of the reference time width of said reference timing pulse; a first counter connected to said synchronization circuit whereby the number of said detector output pulses generated during said counting period is counted repeatedly for each said counting period; a second counter connected to said synchronization circuit whereby the number of said reference pulses generated during said counting period is counted repeatedly for each said counting period; a divider circuit connected to said first and second counters whereby every time said counting period terminates, the count of said first counter is divided by the count of said second counter to obtain a displacement speed; and a subtractor circuit connected to said divider circuit whereby every time a displacement speed is computed by said divider circuit, a subtraction is performed on said computed displacement speed and a just previously obtained displacement speed to determine an acceleration or deceleration of said detected displacement speed.
Claim 2
Dependent Claim
315 words
A digital differentiation circuit for differentiating a frequency proportional to a detected displacement speed, comprising: a reference pulse generating circuit for generating reference pulses having a predetermined frequency; a displacement speed detector for generating output pulses having a frequency proportional to a detected displacement speed; a timing pulse generating circuit for recurrently generating a reference timing pulse having a predetermined reference time width; a synchronization circuit connected to said timing pulse generating circuit, said reference pulse generating circuit and said displacement speed detector whereby the leading edge of said reference timing pulse is synchronized with the leading edge of said detector output pulse and the leading edge of said reference pulse to continuously generate said reference pulse and said detector output pulse synchronized with each other during a counting period extending from the leading edge of said synchronized reference timing pulse to the trailing edge thereof which was extended to the first leading edge of said detector output pulse generated after the termination of the reference time width of said reference timing pulse; a first counter connected to said synchronization circuit whereby the number of said detector output pulses generated during said counting period is counted repeatedly for each said counting period; a second counter connected to said synchronization circuit whereby the number of said reference pulses generated during said counting period is counted repeatedly for each said counting period; a divider circuit connected to said first and second counters whereby every time said counting period terminates, the count of said first counter is divided by the count of said second counter to obtain a displacement speed; and a subtractor circuit connected to said divider circuit whereby every time a displacement speed is computed by said divider circuit, a subtraction is performed on said computed displacement speed and a just previously obtained displacement speed to determine an acceleration or deceleration of said detected displacement speed.
Claim 3
Dependent Claim
91 words
A digital differentiation circuit according to claim 1 further comprising an initial value setting circuit connected between said displacement speed detector and said synchronization circuit, whereby when a displacement speed detected by said displacement speed detector is smaller than a predetermined value, a predetermined pulse of a frequency lower than a predetermined value is applied as an output pulse of said displacement speed detector, whereas when said detected displacement speed is greater than said predetermined value, the output pulse of said displacement speed detector is directly applied to said synchronization circuit.
Claim 4
Dependent Claim
30 words
A digital differentiation circuit according to claim 1, wherein said displacement speed detector comprises a speed sensor for generating output pulses having a frequency corresponding to a detected vehicle speed.
Claim 5
Dependent Claim
33 words
A digital differentiation circuit according to claim 3, wherein said divider circuit is provided with a displacement speed output terminal for delivering to the outside a dIsplacement speed computed by said divider circuit.
Claim 6
Dependent Claim
275 words
A digital differentiation circuit according to claim 1, wherein said synchronization circuit comprises a detector output pulse synchronizing flip-flop having a clock terminal connected to said reference pulse generating circuit, an input terminal connected to said displacement speed detector and an output terminal whereby said detector output pulse having the leading edge thereof synchronized with the leading edge of said reference pulse is generated at said output terminal, a reference timing pulse synchronizing flip-flop having a clock terminal connected to the output of said detector output pulse synchronizing flip-flop, an input terminal connected to said timing pulse generating circuit and an output terminal whereby the leading edge of said reference timing pulse is synchronized with the leading edge of said synchronized detector output pulse and the trailing edge of said reference timing pulse is extended to the leading edge of said synchronized detector output pulse generated immediately after the termination of the reference time width of said reference timing pulse to produce an extended synchronized reference timing pulse at said output terminal, a first logic gate circuit having input terminals respectively connected to said flip-flops and an output terminal connected to said first counter and adapted to be opened by said synchronized reference timing pulse to apply said synchronized detector output pulses to said first counter, and a second logic gate circuit having a first input terminal connected to said reference timing pulse synchronizing flip-flop, a second input terminal connected to said reference pulse generating circuit and an output terminal connected to said second counter and adapted to be opened by said synchronized reference timing pulse to apply said reference pulses to said second counter.
Claim 7
Dependent Claim
176 words
A digital differentiation circuit according to claim 5, wherein said second counter has a reset pulse output terminal provided at a selected one of the bit positions thereof for producing a reset pulse and a reset terminal, and wherein said timing pulse generating circuit comprises a timing setting counter having an input connected to said reference pulse generating circuit, a reset terminal connected to the output terminal of said reference timing time synchronizing flip-flop and an output terminal connected to the reset terminal of said second counter, said timing setting flip-flop being adapted to be reset by said synchronized reference timing pulse to count the number of said reference pulses and produce an output at said output terminal thereof when said count thereof reaches a predetermined value, and a timing setting flip-flop having a set terminal connected to the output terminal of said timing setting counter, a reset terminal connected to the reset pulse output terminal of said second counter and an output terminal connected to the input terminal of said reference timing pulse synchronizing flip-flop.
Claim 8
Dependent Claim
104 words
A digital differentiation circuit according to claim 6, wherein said first counter is provided with a reset terminal connected to the output terminal of said timing setting counter, and said timing pulse generating circuit includes a division controlling logic circuit connected between said timing setting counter and said divider circuit to bring said divider circuit into operation for a predetermined period of time after the resetting of said timing setting counter, and a subtraction controlling logic circuit connected between said timing setting counter and said subtractor circuit to bring said subtractor circuit into operation after the termination of the division by said divider circuit.
Claim 9
Dependent Claim
30 words
A digital differentiation circuit according to claim 2, wherein said displacement speed detector comprises a speed sensor for generating output pulses having a frequency corresponding to a detected vehicle speed.
Claim 10
Dependent Claim
129 words
A digital differentiation circuit according to claim 7, wherein said displacement Speed detector comprises a speed sensor for generating output pulses having a frequency corresponding to a detected vehicle speed, and there is further provided an initial value setting circuit connected between said speed sensor and the input terminal of said detector output pulse synchronizing flip-flop whereby when a speed detected by said speed sensor is smaller than a predetermined value, a predetermined pulse signal of a frequency smaller than a predetermined one is applied as a detector output pulse to the input terminal of said detector output pulse synchronizing flip-flop, whereas when said detected speed is greater than said predetermined value, the output pulse of said speed sensor is directly applied to said detector output pulse synchronizing flip-flop.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-30 | 1978-12-30 | 1979-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-30 | 1982-12-30 | 1983-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-30 | 1986-12-30 | 1987-07-01 | $7700.00 | Window Closed / Lapsed |