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US3891864A Expired / Lapsed US ⏱️ 0.0 years remaining

Josephson junction logic element

Assignee: International Business Machines Corp
•
Filing: 1973-11-02
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Granted: 1975-06-24
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Expires: 1993-11-02
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Abstract

Abstract Logic elements comprising resettable Josephson junctions cooperating with matched transmission lines have input circuit inductances connected to reversible Josephson devices which are so small that a flux of less than one flux quantum only can be trapped therein preventing the continued circulation of supercurrent in the inductance after removal of the input signals from the associated reversible Josephson junctions. The resettable junctions are designed such that upon removal of the input or control field from the resettable Josephson junctions connected to the transmission line, the a.c. voltage which is generated across said junction, is larger than the timeaverage d.c. voltage across said junction when switched to itss state of normal conductance so that, after removal of the input or control field from said junction, the d.c. voltage is caused to lock back to zero, thus resetting the element. Circuit parameters for achieving resettability without interrupting gate current are given. Logic circuits including AND, OR and NOT circuits are described and the conditions for the operation of such circuits which include both resettable and reversible Josephson devices are also given.

Inventors

  • 👤 Pierre Leopold Gueret

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 08:56
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/195; H03K19/1952; G; G11; G11C; G11C11/00; G11C11/21; G11C11/44; Y; Y10; Y10S; Y10S505/00; Y10S505/825; Y10S505/856; Y10S505/857; Y10S505/858

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 48 words
A Josephson junction logic circuit comprising an output circuit having at least a single resettable Josephson device connected to a transmission line which is terminated with its characteristic impedance and having an input circuit coupled to said device, said output circuit having parameters which meet the following criteria:
Claim 2
Dependent Claim 48 words
A Josephson junction logic circuit comprising an output circuit having at least a single resettable Josephson device connected to a transmission line which is terminated with its characteristic impedance and having an input circuit coupled to said device, said output circuit having parameters which meet the following criteria:
Claim 3
Dependent Claim 165 words
A Josephson junction logic circuit according to claim 1, further including another inductance connected in parallel with said input circuit, the current through said input circuit controlling said at least a resettable Josephson junction, both of said inductances being connected to a source of bias current, said input circuit and said another inductance having parameters such that, in the absence of a signal from said signal means, said bias current is divided between said inductances resulting in a control current sufficient to keep said resettable Josephson junction in its voltage state, thereby generating an output in said transmission line and, such that, upon application of a signal from said signal means, current in said input circuit is reduced to a value insufficient to maintain said resettable Josephson junction in its voltage state, causing said resettable Josephson junction to switch to its zero voltage state, thereby eliminating an output signal in said transmission line and wherein the logic circuit parameters to ensure reversibility meet the conditions:
Claim 4
Dependent Claim 124 words
A Josephson logic circuit according to claim 1, wherein said input circuit includes a plurality of reversible Josephson devices electrically connected therein, a plurality of signal means each one of said signal means being electrically coupled to a reversible Josephson junction device, at least an inductance electrically connected to said plurality of reversible Josephson devices, said inductance having a value that, at least in the fundamental mode, where N 0, only less than one flux quantum can be trapped by said inductance and wherein Ibo/imo< pi 1 lambda where Ibo is the bias current supplied to said reversible junctions, lambda is proportional to the inductance L and, N is the maximum number of flux quanta, phi o, which can be trapped in the inductance.
Claim 5
Dependent Claim 74 words
A Josephson logic circuit according to claim 3, wherein said plurality of reversible Josephson devices are disposed in parallel in said input circuit, and said inductance is connected in parallel with said plurality of reversible Josephson devices, and has a value such that the current flowing therethrough when all of said plurality of signal means are energized assumes a magnitude sufficient to switch said at least a single resettable Josephson junction under the conditions:
Claim 6
Dependent Claim 105 words
A Josephson logic circuit according to claim 3, wherein said plurality of reversible Josephson devices are disposed in series in said input circuit and said inductance is disposed in parallel with said plurality of reversible Josephson devices, the condition of said circuit being such that upon activation of any one of said signal means, the current transferred into said inductance is sufficient to switch said resettable Josephson junction into its voltage state so as to produce an output signal in said transmission line and that said resettable junction switches back to the zero voltage state when said input signal ceases, in accordance with the criteria:

References Cited (Backward Citations)

US3564351A Cited
US3573662A Cited
US3758795A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-06-23 1978-12-23 1979-06-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-06-23 1982-12-23 1983-06-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-06-23 1986-12-23 1987-06-24 $7700.00 Window Closed / Lapsed

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