US3890469A
Expired / Lapsed
US
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Time division switching system
Assignee: AG Communication Systems Corp
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Filing: 1973-12-04
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Granted: 1975-06-17
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Expires: 1993-12-04
Abstract
Abstract A plurality of 24-channel, 8-bit time division multiplex carrier lines are inserted with coding data in each channels thereof to identify the PCM data being transmitted. A first multiplexer unit multiplexes and distributes the PCM data and the address coding data of each channel of a predetermined number of the multiplex lines onto a supermultiplexed highway carrier known as a long digital link. Preselected channels of the supermultiplexed highway are used to carry a special channel identification pattern inserted by a channel identification inserter operating within the first multiplexer unit. A channel aligner associated with the supermultiplexed highway is used to recognize the special pattern and align all data for being inputted to a time switch which receives a plurality of the supermultiplexed highways. The time switch includes a second multiplexer unit and a number of input buffer memory stores for distrubuting and storing the PCM data according to the coding of the channel address data to achieve a lower channel occupancy level per line of the PCM data as PCM information is presented to the input ports of a space switching network on a greater plurality of lines than the supermultiplexed input lines.
Inventors
- 👤 Michael J Kelly
- 👤 Satyan G Pitroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:48
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/06
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
271 words
A time division switching system comprising: a plurality of input time division multiplex lines carrying 24 channel multiplexed PCM data, a space switching network having a different plurality of input and output ports associated therewith and output multiplex lines connected to said output ports, network inlet means receiving said input multiplex lines and providing synchronization and frame detection for said multiplexed PCM data, said network inlet means including channel address data generator means for inserting channel address data to accompany said multiplexed PCM data, means for multiplexing and distributing on a plurality of supermultiplexed lines said PCM data and said channel address data to provide therefrom a supermultiplexed time frame format and including channel indentification inserter means for inserting channel indentification coding in said supermultiplexed format channel aligner means cumulatively receiving said supermultiplexed format for separately outputting said PCM data and said channel address data, said channel aligner means referencing the selection of said PCM and said channel address data from said supermultiplexed format according to said channel identification coding, means for distributing said PCM data according to the coding of said channel address data, said distributing thereof providing another multiplexed time frame format having a lower channel occupancy level per line than said supermultiplexed format and distributed on a plurality of multiplex lines greater than said number of supermultiplexed lines, means for storing said PCM data as distributed, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said other multiplexed time frame format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
Claim 2
Dependent Claim
271 words
A time division switching system comprising: a plurality of input time division multiplex lines carrying 24 channel multiplexed PCM data, a space switching network having a different plurality of input and output ports associated therewith and output multiplex lines connected to said output ports, network inlet means receiving said input multiplex lines and providing synchronization and frame detection for said multiplexed PCM data, said network inlet means including channel address data generator means for inserting channel address data to accompany said multiplexed PCM data, means for multiplexing and distributing on a plurality of supermultiplexed lines said PCM data and said channel address data to provide therefrom a supermultiplexed time frame format and including channel indentification inserter means for inserting channel indentification coding in said supermultiplexed format channel aligner means cumulatively receiving said supermultiplexed format for separately outputting said PCM data and said channel address data, said channel aligner means referencing the selection of said PCM and said channel address data from said supermultiplexed format according to said channel identification coding, means for distributing said PCM data according to the coding of said channel address data, said distributing thereof providing another multiplexed time frame format having a lower channel occupancy level per line than said supermultiplexed format and distributed on a plurality of multiplex lines greater than said number of supermultiplexed lines, means for storing said PCM data as distributed, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said other multiplexed time frame format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
Claim 3
Dependent Claim
63 words
A time division switching system as claimed in claim 1 wherein said PCM data and said channel address data occupy x out of every y channels and the channel address coding controls said distributing means to redistribute to said storage means in a load balancing pattern of z out of every y channels wherein x is greater than z and less than y.
Claim 4
Dependent Claim
101 words
A time division switching system as claimed in claim 2 wherein i number of input multiplex lines are multiplexed by said multiplexing and distributing means onto a selected one of n number of long digital carrier links for carrier transmission of said supermultiplexed time frame format having y number of repeating channels, and the PCM data on said n number of carrier links is redistributed by said distributing means to m number of storage means, each thereof having y number of storage positions to accept said PCM data therein wherein i is less than n and n is less than m.
Claim 5
Dependent Claim
42 words
A time division switching system as claimed in claim 3 wherein i is equal to 5, n is equal to 7, m is equal to 8, y is equal to 128, x is equal to 120 and z is equal to 105.
Claim 6
Dependent Claim
77 words
A time division switching system as claimed in claim 1 wherein said supermultiplexed format is comprised of repeating channel time frames of 128 channels of 16 bits each with said PCM data and said channel address data comprised of 8 bits and 7 bits of every repeating channel thereof, said channel identification pattern is comprised of 15 bits of every 16th repeating channel thereof and each 16th bit of every repeating channel comprises a selected parity bit.
Claim 7
Dependent Claim
102 words
A time division switching system as claimed in claim 5 wherein said channel aligner means is comprised of a first storaGe register means which is adapted to accumulate said PCM and said channel address data when activated, binary counter means for activating said first storage register and for causing said first storage register to shift the accumulated data thereof upon the occurrence of every repeating channel when said binary counter means is activated by the occurrence of said channel identification coding, and a second storage register means adapted to receive said accumulated PCM and channel address data and provide separate outputs therefor.
Claim 8
Dependent Claim
123 words
A time division switching system as claimed in claim 1 wherein said means for storing said PCM data is comprised of a plurality of input buffer memory devices, each thereof having a plurality of memory stores to correspond to the maximum number of channels of said supermultiplexed time frame format, said plurality of memory stores being grouped into a number of blocks of said memory stores and said number corresponding to said plurality of memory devices, and the least significant bits of said channel address data are used to determine which memory device will be distributed to and the most significant bits of said channel address data are used to determine which memory stores will be distributed to within the selected memory device.
Claim 9
Dependent Claim
41 words
A time division switching system as claimed in claim 7 wherein said distributing means is a multiplexer means and includes multiplexer address coding data which is used to determine which memory block of said selected memory device will be distributed to.
Claim 10
Dependent Claim
262 words
In a communication switching system, a plurality of input time division multiplex lines carrying PCM data, a switching network having a plurality of inlet ports and a corresponding plurality of outlet ports thereto, line interface means for synchronizing and frame aligning said incoming PCM data, channel address generator means for providing channel address coding data for insertion with said PCM data, a plurality of long digital carrier links, means for multiplexing and distributing said PCM data and said channel address data onto selected ones of said long digital links for transmission therealong, channel identification means for repeatedly inserting a channel identification coding pattern with said PCM data and said channel address data, channel aligner means for aligning the transmission of said PCM data and said channel address data with the repeating occurrences of said channel identification pattern, a plurality of input buffer memory means, means for distributing said PCM data to said input buffer means for storage therein according to the coding of said channel address data, said distributing thereof providing a multiplexed time frame format on a plurality of multiplex lines having a lower channel occupancy level per line than exists on either said input multiplex lines or said long digital links distributed on a plurality of multiplex lines greater than said plurality of long digital link lines, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said lower occupancy level time frame format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
Claim 11
Dependent Claim
262 words
In a communication switching system, a plurality of input time division multiplex lines carrying PCM data, a switching network having a plurality of inlet ports and a corresponding plurality of outlet ports thereto, line interface means for synchronizing and frame aligning said incoming PCM data, channel address generator means for providing channel address coding data for insertion with said PCM data, a plurality of long digital carrier links, means for multiplexing and distributing said PCM data and said channel address data onto selected ones of said long digital links for transmission therealong, channel identification means for repeatedly inserting a channel identification coding pattern with said PCM data and said channel address data, channel aligner means for aligning the transmission of said PCM data and said channel address data with the repeating occurrences of said channel identification pattern, a plurality of input buffer memory means, means for distributing said PCM data to said input buffer means for storage therein according to the coding of said channel address data, said distributing thereof providing a multiplexed time frame format on a plurality of multiplex lines having a lower channel occupancy level per line than exists on either said input multiplex lines or said long digital links distributed on a plurality of multiplex lines greater than said plurality of long digital link lines, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said lower occupancy level time frame format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
Claim 12
Dependent Claim
286 words
A communication switching system comprising a plurality of input time division multiplex lines carrying PCM data arranged in repeating 24-channel 8-bit time frame format, said plurality comprised of n groups of i where i is less than n, channel address generator means for providing channel address coding data to be inserted with each 8-bit sample of said PCM data, n number of long digital carrier links, means for selectively multiplexing and distributing said PCM data and said channel address data onto said carrier links for transmission therealong, channel identification means for intermittently inserting a channel identification coding pattern with said PCM data and said channel address data, n Number of channel aligner means for aligning the transmission of said PCM data and said channel address data with the repeating occurrences of said channel identification pattern, m number of input buffer memory devices where m is greater than n, means for distributing said PCM data to said input buffer memory devices for storage according to the coding of said channel address data, said distributing thereof being according to a multiplexed time frame format on m multiplex lines having a lower channel occupancy level per line than exists on either said input multiplex lines or said long digital links distributed on a plurality of multiplex lines, m, greater than said number, n, of long digital links, m number of output buffer memory devices, a switching network having m number of inlet ports and outlet ports thereto, respectively, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said lower occupancy level format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
Claim 13
Dependent Claim
286 words
A communication switching system comprising a plurality of input time division multiplex lines carrying PCM data arranged in repeating 24-channel 8-bit time frame format, said plurality comprised of n groups of i where i is less than n, channel address generator means for providing channel address coding data to be inserted with each 8-bit sample of said PCM data, n number of long digital carrier links, means for selectively multiplexing and distributing said PCM data and said channel address data onto said carrier links for transmission therealong, channel identification means for intermittently inserting a channel identification coding pattern with said PCM data and said channel address data, n Number of channel aligner means for aligning the transmission of said PCM data and said channel address data with the repeating occurrences of said channel identification pattern, m number of input buffer memory devices where m is greater than n, means for distributing said PCM data to said input buffer memory devices for storage according to the coding of said channel address data, said distributing thereof being according to a multiplexed time frame format on m multiplex lines having a lower channel occupancy level per line than exists on either said input multiplex lines or said long digital links distributed on a plurality of multiplex lines, m, greater than said number, n, of long digital links, m number of output buffer memory devices, a switching network having m number of inlet ports and outlet ports thereto, respectively, and means for controlling the transferring of stored PCM data to said switching network inlet ports according to said lower occupancy level format and controlling said switching network for switching said PCM data from said inlet to said outlet ports thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-16 | 1978-12-16 | 1979-06-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-16 | 1982-12-16 | 1983-06-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-16 | 1986-12-16 | 1987-06-17 | $7700.00 | Window Closed / Lapsed |