Method and system to protect electronic switching components

Claim 2

Method of protecting an electronic semiconductor switching element (11) against short circuits in a load (10) connected in series therewith, comprising generating a test pulse upon connection of the load (10); connecting said test pulse to the switching element (11) to render said switching element conductive; testing the voltage at the junction of the switching element (11) and the load (10) and blocking the switching element (11), or permitting the switching element to remain conductive, in dependence on the level of the sensed test pulse.

Claim 3

Method according to claim 1, further comprising the step of commanding, by logic connection, the sequence of the steps set forth in claim 1.

Claim 4

Method according to claim 1, wherein the step of generating the test pulse comprises driving a semiconductor device heavily into saturation to provide, upon turn-off of said device, a time delay; wherein the step of Connecting the test pulse to the switching element (11) comprises connecting said test pulse both to said semiconductor device and to said semiconductor switching element, to close the switch during the re-combination time period of the semiconductor device.

Claim 5

Protective circuit for a semiconductor switching element (11) to protect the element against short circuits in a load (10) connected in series therewith, and to an energized source of supply (12, 14) comprising means (20, 21, 22) generating a momentary test pulse upon connection of the load (10) to the energized source of supply; means (21) connecting said test pulse to the switching element (11) and controlling said switching element (11) to become conductive to thereby connect the load (10), and the conductive switching element in series therewith, to the energized source of supply; means (19, 20, 18) sensing the voltage at the junction of the switching element (11) upon conduction of the switching element; and means (16, 17, 18) controlling continued conduction of the switching element (11) upon termination of the test pulse in accordance with sensed voltage at the junction of the switching element (11) and the load (10).

Claim 6

Protective circuit for a semiconductor switching element (11) to protect the element against short circuits in a load (10) connected in series therewith, and to an energized source of supply (12, 14) comprising means (20, 21, 22) generating a momentary test pulse upon connection of the load (10) to the energized source of supply; means (21) connecting said test pulse to the switching element (11) and controlling said switching element (11) to become conductive to thereby connect the load (10), and the conductive switching element in series therewith, to the energized source of supply; means (19, 20, 18) sensing the voltage at the junction of the switching element (11) upon conduction of the switching element; and means (16, 17, 18) controlling continued conduction of the switching element (11) upon termination of the test pulse in accordance with sensed voltage at the junction of the switching element (11) and the load (10).

Claim 7

Circuit according to claim 4, wherein said control means includes an AND-gate (17, 18) to render said switching element conductive if both inputs to said AND-gate are energized; and an OR-gate (18, 19, 21) connected to render one of the inputs of the AND-gate conductive if: (a) said sensing means senses a voltage at the junction of the switching element and the load indicative of a predetermined voltage drop across the load; or (b) said test pulse persists.

Claim 8

Circuit according to claim 5, wherein the AND-gate comprises two switching transistors (17, 18) having their emitter-collector paths connected in series, the output of the AND-gate controlling conduction of said switching element; the inputs to said AND-gates comprising connections to the bases of said switching transistors, one of said switching transistors (17) being controlled by an ON-OFF signal commanding connection, or disconnection of the switching element and the second switching transistor (18) being controlled by said OR-gate.

Claim 9

Circuit according to claim 6, wherein the OR-gate includes a connecting transistor (22), an input transistor (27) is provided, said input transistor controlling the conductive state of said connecting transistor.

Claim 10

Circuit according to claim 7, wherein the input transistor (27) controls conduction of said first switching transistor (17) in dependence on the presence, or absence of the ON-OFF command signal.

Claim 11

Circuit according to claim 7, wherein the connecting transistor (22) is connected to the input transistor to be conductive when the input transistor has an OFF-command signal applied thereto, and means (20, 21) connecting said transistor in circuit with the source of supply to conduct heavily in the saturated region; said input transistor (27) being connected to said connecting transistor to tend to render said connecting transistor non-conductive upon having an ON-command signal applied thereto, the time delay between actual turn-off of the connecting transistor and the blocking signal derived from said input transistor forming said test pulse.

Claim 12

Circuit according to claim 4, further comprising a Zener diode (15) connected in parallel to the switching path of said switching element (11).

Claim 13

Circuit according to claim 4, further comprising a current-limiting resistor (13) in series connection with the main current switching path of the switching element (11).

Claim 14

Circuit according to claim 11, wherein the value of said current-limiting resistor (13) is small with respect to the internal resistance of the load (10) to be connected to the switching element (11).

Claim 15

Circuit according to claim 6, wherein the means sensing the voltage at the junction of the switching element and the load compRises a resistor (19) connecting said junction with the base of the other of said switching transistors included in the AND-gate.

Claim 16

Circuit according to claim 8, further comprising a diode (26) connected in series with the switching path of the input transistor (27), and a coupling resistor (30) connecting the junction of said diode and said switching transistor to the control electrode of the first switching transistor (17) included in said AND-gate.

Claim 17

Circuit according to claim 14, further comprising resistance means connected between the source of supply (12) and said diode, the junction between said resistance means and the diode being coupled (23) to the coupling transistor (22).

Claim 18

Circuit according to claim 14, further comprising a second diode (26) coupling the diode (26) to the base of the connecting transistor (22), and a resistor (24) connecting the base to the other terminal of the source of supply to form a base voltage divider for the coupling transistor (22).

Claim 19

Circuit according to claim 9, further comprising a coupling resistor (21) connecting the output of said coupling transistor (22) to the control electrode of the second switching transistor (18) included in said AND-gate, and forming one input of the OR-gate thereto.

Claim 20

Circuit according to claim 6, further comprising resistance means (16) connected in series with the switching paths of said switching transistors (17, 18) included in said AND-gate, a Zener diode (15) connected in series with said resistance means (16); and a connection from the junction of said Zener diode (15) and said resistance means (16) to the control terminal of said switching element (11) and forming said means controlling the conduction of the transistor.

Claim 21

Circuit according to claim 4, wherein said means generating the test pulse upon connection of the circuit to the load comprises a connecting transistor (22) connected to be normally conductive in heavily saturated condition, and an input transistor (27) changing state upon command of an input signal (29), the re-combination time delay of said heavily conducting connecting transistor (27) after change-of-state of said input transistor, upon having a signal applied thereto, providing said test pulse; the connecting means connecting said test pulse to said switching element comprising an AND-gate (17, 18) rendered conductive upon occurrence a. an input command signal rendering said semiconductor switching element (11) conductive to turn the circuits ON, and b. i. persistance of said test pulse during the re-combination time period of said connecting transistor (22) or ii. sensing of voltage at the junction of the switching element and the load indicative of proper internal resistance of the load by said sensing means.

Claim 22

Circuit according to claim 4 wherein the time duration of the test pulse is in the order of the short-time maximum current of the switching element (11).

Claim 23

Circuit according to claim 20 wherein said time duration is in the order of one microsecond.