US3887918A
Expired / Lapsed
US
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Multi-level digital coincidence detection
Assignee: TDK Micronas GmbH
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Filing: 1973-05-09
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Granted: 1975-06-03
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Expires: 1993-05-09
Abstract
Abstract A multi-level coincidence detector for use in a radar system which transmits relatively long pulses each divided into a plurality of successive subpulses, each discretely digitally phase coded. In order to effect pulse compression on reception, the transmitted codes are stored, and received bipolar video is hard limited and examined by a delay-line or shift register coincidence detector arrangement against the stored code in groups, each containing a fraction of the subpulses of the total transmitted pulse duration. Each of the detectors at this first level coincidence detection operates to provide a first or second digital output level based on affirmative comparison of received vs. stored codes during that group (fraction of the subpulses). A second level coincidence detector examines the output of each coincidence detector of this first level and provides a digital output, for example, corresponding to presence of signal when a predetermined fraction of the first level coincidence detectors have indicated presence of signal.
Inventors
- 👤 John S Bailey
- 👤 David E Hammers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:06
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/02; G01S13/06; G01S13/08; G01S13/10; G01S13/26; G01S13/28; G01S13/284; G01S13/288
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
329 words
In a radar system having means for transmitting relatively long pulses each subdivided into a plurality of N substantially equal duration successive subpulses each coded in first or second radio frequency phase condition according to a predetermined program, and pulse echo receiving means, pulse compression means comprising: means responsive to said transmitting means for storing the code of said transmitted pulses as a series of one-bit digital codes corresponding discretely to said subpulses; phase detection means responsive to said receiving means for producing a sequence of bi-polar video pulses the polarities of which correspond discretely to said first and second radio frequency phase conditions; means responsive to said phase detection means for converting said video polarities to a one-bit digital code corresponding to each of said subpulses at the output thereof; delay means responsive to said one-bit code, said delay means having a transmission time at least as long as said relatively long transmitted pulses, said delay means having a number of taps corresponding to the number of said successive subpulses, said taps being spaced by a time substantially equal to the duration of one of said increments; a first level correlator comprising a first bank of G coincidence detectors, said coincidence detectors each connected to correlate a different predetermined fraction of the plurality of N subpulses of said transmitted pulse against the corresponding fraction of said subpulses in said means for storing the code of said transmitted pulses, said coincidence detectors connecting between corresponding groups of taps on said delay means and said means for storing the code of said transmitted pulses, said coincidence detectoRs each producing a single output providing a one bit code representing correlation success, or the lack of it, within the corresponding detector; and a second level correlator comprising a second bank of coincidence detectors responsive to the outputs of said first level correlator for producing a one bit output representative of at least two successes in the outputs of said G coincidence detectors.
Claim 2
Dependent Claim
329 words
In a radar system having means for transmitting relatively long pulses each subdivided into a plurality of N substantially equal duration successive subpulses each coded in first or second radio frequency phase condition according to a predetermined program, and pulse echo receiving means, pulse compression means comprising: means responsive to said transmitting means for storing the code of said transmitted pulses as a series of one-bit digital codes corresponding discretely to said subpulses; phase detection means responsive to said receiving means for producing a sequence of bi-polar video pulses the polarities of which correspond discretely to said first and second radio frequency phase conditions; means responsive to said phase detection means for converting said video polarities to a one-bit digital code corresponding to each of said subpulses at the output thereof; delay means responsive to said one-bit code, said delay means having a transmission time at least as long as said relatively long transmitted pulses, said delay means having a number of taps corresponding to the number of said successive subpulses, said taps being spaced by a time substantially equal to the duration of one of said increments; a first level correlator comprising a first bank of G coincidence detectors, said coincidence detectors each connected to correlate a different predetermined fraction of the plurality of N subpulses of said transmitted pulse against the corresponding fraction of said subpulses in said means for storing the code of said transmitted pulses, said coincidence detectors connecting between corresponding groups of taps on said delay means and said means for storing the code of said transmitted pulses, said coincidence detectoRs each producing a single output providing a one bit code representing correlation success, or the lack of it, within the corresponding detector; and a second level correlator comprising a second bank of coincidence detectors responsive to the outputs of said first level correlator for producing a one bit output representative of at least two successes in the outputs of said G coincidence detectors.
Claim 3
Dependent Claim
329 words
In a radar system having means for transmitting relatively long pulses each subdivided into a plurality of N substantially equal duration successive subpulses each coded in first or second radio frequency phase condition according to a predetermined program, and pulse echo receiving means, pulse compression means comprising: means responsive to said transmitting means for storing the code of said transmitted pulses as a series of onebit digital codes corresponding discretely to said subpulses; phase detection means responsive to said receiving means for producing a sequence of bi-polar video pulses the polarities of which correspond discretely to said first and second radio frequency phase conditions; means responsive to said phase detection means for converting said video polarities to a one-bit digital code corresponding to each of said subpulses at the output thereof; delay means responsive to said one-bit code, said delay means having a transmission time at least as long as said relatively long transmitted pulses, said delay means having a number of taps corresponding to the number of said successive subpulses, said taps being spaced by a time substantially equal to the duration of one of said increments; a first level correlator comprising a first bank of G coincidence detectors, said coincidence detectors each connected to correlate a different predetermined fraction of the plurality of N subpulses of said transmitted pulse against the corresponding fraction of said subpulses in said means for storing the code of said transmitted pulses, said coincidence detectors connecting between corresponding groups of taps on said delay means and said means for storing the code of said transmitted pulses, said coincidence detectoRs each producing a single output providing a one bit code representing correlation success, or the lack of it, within the corresponding detector; and a second level correlator comprising a second bank of coincidence detectors responsive to the outputs of said first level correlator for producing a one bit output representative of at least two successes in the outputs of said G coincidence detectors.
Claim 4
Dependent Claim
329 words
In a radar system having means for transmitting relatively long pulses each subdivided into a plurality of N substantially equal duration successive subpulses each coded in first or second radio frequency phase condition according to a predetermined program, and pulse echo receiving means, pulse compression means comprising: means responsive to said transmitting means for storing the code of said transmitted pulses as a series of onebit digital codes corresponding discretely to said subpulses; phase detection means responsive to said receiving means for producing a sequence of bi-polar video pulses the polarities of which correspond discretely to said first and second radio frequency phase conditions; means responsive to said phase detection means for converting said video polarities to a one-bit digital code corresponding to each of said subpulses at the output thereof; delay means responsive to said one-bit code, said delay means having a transmission time at least as long as said relatively long transmitted pulses, said delay means having a number of taps corresponding to the number of said successive subpulses, said taps being spaced by a time substantially equal to the duration of one of said increments; a first level correlator comprising a first bank of G coincidence detectors, said coincidence detectors each connected to correlate a different predetermined fraction of the plurality of N subpulses of said transmitted pulse against the corresponding fraction of said subpulses in said means for storing the code of said transmitted pulses, said coincidence detectors connecting between corresponding groups of taps on said delay means and said means for storing the code of said transmitted pulses, said coincidence detectoRs each producing a single output providing a one bit code representing correlation success, or the lack of it, within the corresponding detector; and a second level correlator comprising a second bank of coincidence detectors responsive to the outputs of said first level correlator for producing a one bit output representative of at least two successes in the outputs of said G coincidence detectors.
Claim 5
Dependent Claim
69 words
Apparatus according to claim 1 in which said transmitting means includes a pulse coder for encoding the RF phase of said subpulses discretely in either a first phase or a second phase, and said receiving means includes coherent detection means whereby received pulse envelopes are comprised of subpulses having amplitudes determined by said first phase or said second phase in the corresponding transmitted subpulses ahead of said hard limiter.
Claim 6
Dependent Claim
20 words
Apparatus according to claim 2 in which said second phase is shifted 180* RF with respect to said first phase.
Claim 7
Dependent Claim
249 words
In a radar system which includes means for transmitting and means for receiving pulse envelopes comprising a plurality of N subpulses discretely phase coded in accordance with a predetermined code pattern, the combination comprising: an analog-to-digital converter comprising a hard limiter responsive to said received pulse envelopes, said limiter providing the function of a one-bit analog-to-digital converter, whereby said N subpulses are reduced to signals of first or second condition; storage means connected to said transmitting means for storing said code of said transmitted pulse envelope subpulses between successive transmissions; delay means responsive to the output of said analog-to-digital converter, said delay means having a plurality of outputs delay spaced substantially one subpulse duration, the number of said delay means outputs equalling the number of said subpulses in each of said pulse envelopes; means comprising a plurality of G first coincidence detector circuits each responsive to a fraction of said delay means taps and a corresponding fraction of the subpulses of said transmitted code stored by said storage means, said first coincidence detector circuits being adapted to provide an affirmative output signal from the output of each of said G first coincidence detector whenever at least a predetermined number of subpulses from said delay means matches the code of the corresponding subpulses from said second means; and means comprising a second coincidence detector circuit responsive to said first coincidence detector outputs to provide an affirmative output only when at least two of said G first detector outputs are affirmative.
Claim 8
Dependent Claim
249 words
In a radar system which includes means for transmitting and means for receiving pulse envelopes comprising a plurality of N subpulses discretely phase coded in accordance with a predetermined code pattern, the combination comprising: an analog-to-digital converter comprising a hard limiter responsive to said received pulse envelopes, said limiter providing the function of a one-bit analog-to-digital converter, whereby said N subpulses are reduced to signals of first or second condition; storage means connected to said transmitting means for storing said code of said transmitted pulse envelope subpulses between successive transmissions; delay means responsive to the output of said analog-to-digital converter, said delay means having a plurality of outputs delay spaced substantially one subpulse duration, the number of said delay means outputs equalling the number of said subpulses in each of said pulse envelopes; means comprising a plurality of G first coincidence detector circuits each responsive to a fraction of said delay means taps and a corresponding fraction of the subpulses of said transmitted code stored by said storage means, said first coincidence detector circuits being adapted to provide an affirmative output signal from the output of each of said G first coincidence detector whenever at least a predetermined number of subpulses from said delay means matches the code of the corresponding subpulses from said second means; and means comprising a second coincidence detector circuit responsive to said first coincidence detector outputs to provide an affirmative output only when at least two of said G first detector outputs are affirmative.
Claim 9
Dependent Claim
29 words
Apparatus according to claim 4 in which said G first coincidence detector circuits are each responsive to a fraction equal to N/G of said subpulses from said storage means.
References Cited (Backward Citations)
US3427617A
Cited
US3167738A
Cited
US3341845A
Cited
US3480956A
Cited
US3689750A
Cited
US3680100A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-06-02 | 1978-12-02 | 1979-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-06-02 | 1982-12-02 | 1983-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-06-02 | 1986-12-02 | 1987-06-03 | $7700.00 | Window Closed / Lapsed |