US3886528A
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Programmable control apparatus
Assignee: Rockwell Automation Switzerland GmbH
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Filing: 1974-02-25
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Granted: 1975-05-27
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Expires: 1994-02-25
Abstract
Abstract Programmable control apparatus provided with a plurality of addressed program lines each having a respective read-out storage for the preserved storage at addressed storage positions or locations of coded command and address information characterizing the individual steps of a flow diagram. A respective stepping or indexing storage delivers the address signals for the storage positions of the read-out storage. The addressed program blocks and the stepping storages are interconnected through a common program address line, a common command line and a common stepping or indexing-control signal line. Further, a central station or device contains a clock generator which generates in successive periods a respective predetermined number of time-displaced clock signals which do not intersect one another, a cyclically throughcounting program address counter with which there is connected the program address line, a command register with which there is connected the command line, a control logic for the evaluation of decoded command signals and connected by a command-decoding circuit with the command register, and at which control logic there are connected the input stages by means of a common inputinformation line and the output stages by means of a common output-information line, and an address storage (anti-clockwise storage) with random access for a command-dependent storage of program block addresses. Further, for each program block there is provided at least one timing circuit, and during each period of clock signals the program address counter is indexed further by one by means of the first clock signal, by means of the second clock signal the command register is read-in, by means of at least one terminal clock signal according to the momentary program block addresses provided for the relevant program block there is controlled at least one timing circuit, and by means of the remaining clock signals there is controlled the period of the control logic as a function of the read-in command signals, so that during each counting cycle of a program address counter all program blocks are sampled and during each period there is carried out a command.
Inventors
- 👤 Jamshed Irani
- 👤 Eduard End
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:09
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/05; G05B2219/00; G05B2219/10; G05B2219/11; G05B2219/1125; G05B2219/13; G05B2219/13015; G05B2219/13142; G05B2219/14; G05B2219/14089; G05B2219/14112; G05B2219/14143; G05B2219/15; G05B2219/15049
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
414 words
A programmable control apparatus for controlling switching devices according to a number of flow diagrams which are interdependent and/or independent of one another, comprising, in combination, a plurality of addressed input stages for the reception of binary input information signals characteristic of the conditions of the switching devices connected therewith; a plurality of addressed output stages with connections for the switching devices for delivering output-information signals characteristic of switching commands; a central unit with which there are connected, via a common address line, said input stages and said output stages; a plurality of addressed program blocks, each having a respective read-out storage for the preserved storage at addressed storage positions of coded command and address information characteristics of the individual steps of a flow diagram, and a respective stepping storage which delivers the address signals for the storage positions of said read-out storage; a common program address line, a common command line and a common stepping-control signal line, said lines interconnecting said program blocks; said central unit containing: a clock generator generating in successive periods a respective predetermined number of time-displaced clock signals which do not overlap one another; a cyclically through-counting program address counter with which there is connected said program address line, a command register with which there is connected said command line, a control logic for the evaluation of decoded command signals, a command decoding circuit for connecting said control logic with said command register, said input stages being connected with said control logic by means of a common input information line, and said output stages by means of a common output information line; and an address storage with random access for the command-dependent storage of program block addresses; each of said program blocks being provided with at least one timing circuit, wherein during each period of the clock signals by means of a first clock signal said program address counter is indexed by one step, by means of a second clock signal said command register is read in, by means of at least one last clock signal according to the momentary program block address there is controlled at least one of said timing circuits provided for the relevant program block, and by means of the remaining clock signals there is controlled said control logic as a function of the read-in command signal, so that during each counting cycle of said program address counter all of said program blocks are sampled, and during each period there is carried out a command.
Claim 2
Dependent Claim
414 words
A programmable control apparatus for controlling switching devices according to a number of flow diagrams which are interdependent and/or independent of one another, comprising, in combination, a plurality of addressed input stages for the reception of binary input information signals characteristic of the conditions of the switching devices connected therewith; a plurality of addressed output stages with connections for the switching devices for delivering output-information signals characteristic of switching commands; a central unit with which there are connected, via a common address line, said input stages and said output stages; a plurality of addressed program blocks, each having a respective read-out storage for the preserved storage at addressed storage positions of coded command and address information characteristics of the individual steps of a flow diagram, and a respective stepping storage which delivers the address signals for the storage positions of said read-out storage; a common program address line, a common command line and a common stepping-control signal line, said lines interconnecting said program blocks; said central unit containing: a clock generator generating in successive periods a respective predetermined number of time-displaced clock signals which do not overlap one another; a cyclically through-counting program address counter with which there is connected said program address line, a command register with which there is connected said command line, a control logic for the evaluation of decoded command signals, a command decoding circuit for connecting said control logic with said command register, said input stages being connected with said control logic by means of a common input information line, and said output stages by means of a common output information line; and an address storage with random access for the command-dependent storage of program block addresses; each of said program blocks being provided with at least one timing circuit, wherein during each period of the clock signals by means of a first clock signal said program address counter is indexed by one step, by means of a second clock signal said command register is read in, by means of at least one last clock signal according to the momentary program block address there is controlled at least one of said timing circuits provided for the relevant program block, and by means of the remaining clock signals there is controlled said control logic as a function of the read-in command signal, so that during each counting cycle of said program address counter all of said program blocks are sampled, and during each period there is carried out a command.
Claim 3
Dependent Claim
247 words
The control apparatus as defined in claim 1, wherein said central unit includes an internal operating-driving logic and an internal control-driving logic, an external operating and control panel equipped with manual switches and control signal lamps for said operating-driving logic and said control-drivIng logic, said switches including a switch for triggering a resetting signal by means of which said clock generator is blocked through the agency of said operating-driving logic and said program address counter, said command register, said address storage, said timing circuit and said stepping storages of said program blocks are set to null; said manual switches including an operation-mode selector switch for setting different operational modes of the control apparatus; said operation-mode selector switch in one of its switch positions for automatic operation actively switching said clock generator via said operating-driving logic by means of a running signal which can be manually triggered by another switch to the program course for said central unit; and said operation-mode selector switch in its switch position for test operation for the control of commands stored at said program blocks connects said command line via said control-driving logic with said signal lamps, and via said operating-driving logic said program address counter is further indexed by one step by means of a program-address switching signal triggered by still another switch, and by means of command-address switching signal triggered by yet another switch, said stepping storage of said program block designated by the program address is indexed by one step.
Claim 4
Dependent Claim
110 words
The control apparatus as defined in claim 2, further comprising a controlled selector circuit connecting said program address line for the infeed of program block-address signals with said program address counter for the command-independent addressing of said program blocks by address signals of said program address counter, with said command register for the command-dependent addressing of said program blocks by command signals, and for the selective addressing of said program blocks with a transmitter circuit of said operating-driving logic; said manual switches including manual switch means for the output of address signals for activating said transmitter circuit, and signal lamps for indicating the addresses selected by said manual switch means.
Claim 5
Dependent Claim
68 words
The control apparatus as defined in claim 3, wherein for a semi-automatic operation in a further switch position of said operation-mode selector switch, said program address counter is blocked via said operating-driving logic, said manual switch means for addressing a selected program block, said manual switches further including a switch for triggering a start signal for the selected program block for starting the automatic running of a program.
Claim 6
Dependent Claim
70 words
The control apparatus as defined in claim 3, wherein, for the use of a program stored in one of said program blocks as a subroutine, said program address line is connected via said controlled selector circuit with said address storage, and the latter is connected with said command register via a switch element for reading in of an address, and with said program address counter for reading out the address.
Claim 7
Dependent Claim
158 words
The control apparatus as defined in claim 2, wherein a number of said input stages are grouped together into at least one input unit which includes a storage with a respective storage position for each input of said input unit, said storage being connected with said inputs via a respective low-pass filter and a respective contact transducer, said storage for reading in input information signals appearing at said inputs is connected via a reading line with said central unit and via selector circuits and a gate circuit with said common input information line, said gate circuit being controlled by said common address line connected with an address decoder circuit and which address line receives address signals for said command register, wherein the input addresses encompass a respective first address portion for addressing said input units via said address decoder circuit, and a second address portion for addressing the individual inputs of said input units via said selector circuits.
Claim 8
Dependent Claim
140 words
The control apparatus as defined in claim 6, wherein each of said input units includes a further gate circuit for control purposes, by means of which the positions of said storage are connected with a multiconductor control input-information line, and said further gate circuit is controlled by a control-address decoder circuit coupled via a common control-address line with said control-driving logic, wherein the latter, for the selective occupancy of said control address line with control address signals, includes an address transmitter circuit which can be operated by address manual switch means of said manual switches, and further includes switching means by means of which said control input-information line for the indication of the input information appearing at said inputs of the input unit, which is selected by a control address, is connected with at least some of said signal lamps.
Claim 9
Dependent Claim
171 words
The control apparatus as defined in claim 7, wherein a number of said output stages are assembled together into an output unit containing a storage with a respective storage position for each output of said output unit, said storage for the reading-in of command signals being connected via an address decoding circuit with said common address line and said common output information line, and for the occupancy of said outputs of the output unit with switching signals, corresponding to the command signals, said storage is coupled via a switch element and a respective driver stage with controlled switching flanks with said outputs of the output unit, said switch element being controlled by function signals of said operating-driving logic via a function decoding circuit, so that for a switch position of said operation-mode selector switch for automatic and semi-automatic operation there is established a connection of said storage with said outputs of the output unit, and with a switch position of said operation-mode selector switch for test operation said connection is interrupted.
Claim 10
Dependent Claim
83 words
The control apparatus as defined in claim 8, wherein for control purposes each of said output unit has the outputs thereof connected via a control-address decoder circuit with said common control-address line, and via a gate circuit controlled by said address-decoder circuit with a common multi-conductor control-output information line, wherein said control-output information line is connected via switching means at signal lamps for the indication of the output information which appears at said outputs of the output unit selected by the control address.
Claim 11
Dependent Claim
102 words
The control apparatus as defined in claim 9, wherein said control-driving logic for an output test contains test-output signal generator means which can be operated by test-manual switch means, a multiconductor test-output information line connected with said test-output signal generator means, and for each output unit said inputs of the driver stages are connected via said switch element with said test-output information line when said operation-mode selector switch is in its test operation position, so that during test operation by means of said test-manual switch means said outputs of the output unit selected by a control address can be extinguished and set.
Claim 12
Dependent Claim
173 words
The control apparatus as defined in claim 10, wherein for the switch position of said operation-mode selector switch corresponding to test operation said outputs are connected via said switch element with said test-output information line and the input information signals fed to said control logic via said input information line are blocked by a function signal which is delivered in this test switch position of said operation-mode selector switch from said operating-driving logic, so that the program test can be performed without taking into account the input conditions, and that additionally a program test with input conditions is provided wherein in a further switch position of said operation-mode selector switch for manual operation, similar to the test operation, said program address counters and said stepping storages of said program blocks can be stepwise indexed by actuation of given switches of said manual switches, but by means of a function signal of said operation-driving logic there is eliminated the blocking of the input signals, and the outputs are blocked via the associated switch element.
Claim 13
Dependent Claim
233 words
The control apparatus as defined in claim 1, further including a digital time determination provided for each of said timing circuits in which a time-span is determined by a number of timing steps of uniform duration and by downward counting of the number of timing steps to null, and each timing circuit of said program blocks contains a timing-step number storage which can be addressed with its address for receiving binary coded information for the number of timing steps, a common performance logic for said timing step number storage, a subtraction logic with a null detector and a circuit arrangement for generating a timing step signal of uniform timing step duration, the timing step signal of said circuit arrangement being synchronized with the first clock signal of the clock signal period of said clock generator, said performance logic delivering a blocking signal to said clock generator, by means of which the program is blocked for a full cycle and during which cycle, by means of said subtraction logic, said timing-step number storage, which contains timing step number information, is adjusted to the momentarily prevailing newest state, and said null detector, with a storage content which does not equal null, delivers a logical signal 1, and with a storage content which equals null delivers a logical signal 0, by means of which there is blocked the subtraction operation for the relevant timing-step number storage.
Claim 14
Dependent Claim
122 words
The control apparatus as defined in claim 12, wherein said circuit arrangement for generating timing step signals contains a timing unit for generating a network synchronized timing clock signal, a first 1:10 divider circuit with a synchronization circuit controlled by said performance logic, and a second divider circuit for two further 1:10 scaling operations, said circuit arrangement thus delivering timing step signals for three different timing step durations, and said timing circuit for each program block contains a storage unit for receiving binary coded information concerning the momentarily valid timing step duration, wherein by means of the stored timing step duration information, there is determined via said performance logic, which of the three timing step signals is effective at said subtraction logic.
Claim 15
Dependent Claim
115 words
The control apparatus as defined in claim 13, wherein said timing circuit for each program block contains a first pair of timing storages, encompassing a time step duration storage and a time step number storage, and a second pair of timing storages, both pairs of timing storages being addressed with the address of an associated one of said program blocks and being distinguished at said performance logic by characteristic information contained in the commands, and said performance logic for said first pair of timing storages is controlled by the next to last clock signal of the clock signal period, and for said second pair of timing storages it is controlled by the last clock signal.
Claim 16
Dependent Claim
146 words
The control apparatus as defined in claim 14, wherein said program blocks contain a respective condition storage having storage positions at which there can be stored information characterized by binary signals and indicating whether the program of the relevant one of said program blocks is active or not active, whether a subroutine is active or not active, whether said first or said second pair of timing storages is active or not active, and whether an alarm bit has been set or not set, and said condition storage of the associated one of said program blocks is occupied with signals via a common conditioncontrol signal line and a respective gate circuit from a control portion of said control logic, and condition signals of said condition storage are effective at said ceNtral unit via a further gate circuit of each program block and a common condition signal line.
Claim 17
Dependent Claim
39 words
The control apparatus as defined in claim 15, wherein each program block contains at its front face signal lamps at which there are indicated the step number of said stepping storage and the signal occupancy of said condition storage.
References Cited (Backward Citations)
US3475733A
Cited
US3742460A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |