US3886522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vocabulary and error checking scheme for a character-serial digital data processor
Assignee: Unisys Corp
•
Filing: 1974-02-28
•
Granted: 1975-05-27
•
Expires: 1994-02-28
Abstract
Abstract A character-serial electronic digital computer utilizing a four character vocabulary, each character being represented by two binary bits, is structured to process character-serial data arriving at the computer in a manner specified and initiated by the arriving data. Data structures that may represent program or operations to be performed on data arriving at the computer input are stored in the computer''s storage area in the form of nested data structures that may be illustrated as tree structures in which each node of the tree structure represents an operation. Data structures that may represent operands are supplied to the computer also in a nested organization. This operand data addresses a certain node or operation resident in the computer storage area. The linking up of the arriving operand data with its program data triggers execution of the operation. In a case where more than one operand is needed before an operation can be performed, the arrival of a first operand without the second causes storage of the first operand until arrival of the second operand. Arrival of the second operand triggers the operation to begin. This interrelationship of program data and operand data, that is, the dynamic data being linked with the static data to trigger the operation, exists whether the program data is stored and static or the operand data is stored and static. Utilizing a four character vocabulary, to represent data, two of the characters being utilized to indicate the beginning and end of a data field, facilitates the implementation of an error checking technique wherein only sensed characters indicating the beginning and end of a data field are counted. The utilization of beginning and end of data field characters in the data structures consisting of nested data fields permits at will expansion and contraction of the fields within it.
Inventors
- 👤 Robert S Barton
- 👤 Erwin A Hauck
- 👤 Don M Lyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 14:12
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; G06F15/00; G06F15/16; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4482; G06F9/4484; G06F9/4494; H; H04; H04L; H04L1/00; H04L1/004
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
207 words
Error checking means for use in a data processor in which data is commmunicated between various parts of the processor in the form of data structures, each data structure being comprised of a plurality of characters chosen from at least four possible types of characters and each data structure having a format such that the number of a first type of character contained in a data structure has a predetermined relation to the number of a second type of character contained in the data structure, said error checking means comprising: input means to which the characters of a data structure are applied in a character-serial format, first detecting means coupled to said input means for detecting the presence of first types of characters contained in an applied data structure, second detecting means coupled to said input means for detecting the presence of second types of characters contained in an applied data structure, and interpreting means including counting means coupled to said first and second detecting means and responsive to the detection of said first and second types of characters for providing an indication of the occurrence of an error based on the relative numbers of said first and second types of characters contained in the data structure.
Claim 2
Dependent Claim
207 words
Error checking means for use in a data processor in which data is commmunicated between various parts of the processor in the form of data structures, each data structure being comprised of a plurality of characters chosen from at least four possible types of characters and each data structure having a format such that the number of a first type of character contained in a data structure has a predetermined relation to the number of a second type of character contained in the data structure, said error checking means comprising: input means to which the characters of a data structure are applied in a character-serial format, first detecting means coupled to said input means for detecting the presence of first types of characters contained in an applied data structure, second detecting means coupled to said input means for detecting the presence of second types of characters contained in an applied data structure, and interpreting means including counting means coupled to said first and second detecting means and responsive to the detection of said first and second types of characters for providing an indication of the occurrence of an error based on the relative numbers of said first and second types of characters contained in the data structure.
Claim 3
Dependent Claim
49 words
The invention in accordance with claim 1, wherein said counting means are responsive to the detection of said first and second types of characters for providing an output representative of the difference between the numbers of said first and second types of characters contained in an applied data structure.
Claim 4
Dependent Claim
51 words
The invention in accordance with claim 2, wherein said counting means operates to count up in response to the detection of said first type of character by said first detecting means and to count down in response to the detection of said second type of character by said second detecting means.
Claim 5
Dependent Claim
49 words
The invention in accordance with claim 2 wherein a data structure contains an equal number of said first and second types of characters, and wherein said counting means operates to provide an output representative of a zero difference in response to an applied data structure having no error therein.
Claim 6
Dependent Claim
41 words
The invention in accordance with claim 2, wherein a data structure includes a terminating code, and wherein said interpreting means determines the occurrence of an error based upon the output provided by said counting means when said terminating code is detected.
Claim 7
Dependent Claim
29 words
The invention in accordance with claim 2, whereIn said first type of character is a start data character and said second type of character is an end data character.
Claim 8
Dependent Claim
49 words
The invention in accordance with claim 2, wherein said four possible types of characters comprise a start data character, an end data character, a 1 character, and a O character, and wherein said input means is responsive only to said start of data and said end of data characters.
Claim 9
Dependent Claim
26 words
The invention in accordance with claim 7, wherein each character comprises a unique plurality of binary bits which are applied in parallel to said input means.
Claim 10
Dependent Claim
210 words
Error checking means for use in a digital data processor wherein digital data structures are communicated between various parts of the processor in a predetermined character-serial format employing four unique characters with each character being represented by a unique pair of binary bits, said four characters comprising a 1 character, a O character, a start data character, and an end data character, and wherein said data structures each have a format such that the numbers of start and end data characters in each data structure have a predetermined relative relation to one another, said error checking means comprising: a pair of input lines to which the characters of a data structure are serially applied with the pair of bits of each character being applied in parallel on respective ones of said input lines, first detecting means coupled to said input lines for detecting characters having bits representative of start data characters, second detecting means coupled to said input lines for detecting characters having bits representative of end data characters, and interpreting means including counting means coupled to said first and second detecting means for providing an indication of the occurrence of an error based on the relative numbers of start data and end data characters detected in a data structure.
Claim 11
Dependent Claim
210 words
Error checking means for use in a digital data processor wherein digital data structures are communicated between various parts of the processor in a predetermined character-serial format employing four unique characters with each character being represented by a unique pair of binary bits, said four characters comprising a 1 character, a O character, a start data character, and an end data character, and wherein said data structures each have a format such that the numbers of start and end data characters in each data structure have a predetermined relative relation to one another, said error checking means comprising: a pair of input lines to which the characters of a data structure are serially applied with the pair of bits of each character being applied in parallel on respective ones of said input lines, first detecting means coupled to said input lines for detecting characters having bits representative of start data characters, second detecting means coupled to said input lines for detecting characters having bits representative of end data characters, and interpreting means including counting means coupled to said first and second detecting means for providing an indication of the occurrence of an error based on the relative numbers of start data and end data characters detected in a data structure.
Claim 12
Dependent Claim
54 words
The invention in accordance with claim 9, wherein said counting means operates to count in one direction in response to the detection of said start data character by said first detecting means and to count in the other direction in response to the detection of said end data character by said second detecting means.
Claim 13
Dependent Claim
49 words
The invention in accordance with claim 9, wherein a data structure contains an equal number of said start data and end data characters, and wherein said counting means operates to provide an output representative of a zero difference in response to an applied data structure having no error therein.
Claim 14
Dependent Claim
41 words
The invention in accordance with claim 9, wherein a data structure includes a terminating code, and wherein said interpreting means determines the occurrence of an error based upon the output provided by said counting means when said terminating code is detected.
Claim 15
Independent Claim
186 words
A method of providing error checking data in a data processing system, said method comprising the steps of: transmitting data in said data processing system in the form of data structures which are transmitted on pairs of electrical signal conducting paths in a character-serial format employing four unique characters with each character being represented by a unique pair of binary bits which are transmitted in parallel on said pairs of signal paths, said four unique characters comprising a start data character, an end data character, a 1 character, and a 0 character, said data structures being formatted so that the numbers of start and end data characters in each data structure have a predetermined relative relation to one another, detecting characters in a transmitted data structure having bits representative of start data characters, detecting characters in a transmitted data structure having bits representative of end data characters, counting the start data characters and end data characters detected in a transmitted data structure, and generating an error indication based on the relative numbers of said start of data and end data charactErs counted in the data structure.
Claim 16
Independent Claim
186 words
A method of providing error checking data in a data processing system, said method comprising the steps of: transmitting data in said data processing system in the form of data structures which are transmitted on pairs of electrical signal conducting paths in a character-serial format employing four unique characters with each character being represented by a unique pair of binary bits which are transmitted in parallel on said pairs of signal paths, said four unique characters comprising a start data character, an end data character, a 1 character, and a 0 character, said data structures being formatted so that the numbers of start and end data characters in each data structure have a predetermined relative relation to one another, detecting characters in a transmitted data structure having bits representative of start data characters, detecting characters in a transmitted data structure having bits representative of end data characters, counting the start data characters and end data characters detected in a transmitted data structure, and generating an error indication based on the relative numbers of said start of data and end data charactErs counted in the data structure.
Claim 17
Dependent Claim
39 words
The invention in accordance with claim 13, wherein the step of counting comprises counting in one direction in response to detecting a start data character and counting in the opposite direction in response to detecting an end data character.
Claim 18
Dependent Claim
43 words
The invention in accordance with claim 13, wherein a data structure contains an equal number of start data and end data characters, and wherein the step of counting produces a zero count result in response to a data structure having no error therein.
Claim 19
Dependent Claim
38 words
The invention in accordance with claim 13, wherein a data structure includes a terminating code, and wherein the step of generating provides an error indication based upon the results of said counting when said terminating code is detected.
References Cited (Backward Citations)
US3354429A
Cited
US3399394A
Cited
US3652988A
Cited
US3685021A
Cited
US3678222A
Cited
US3689899A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |