Digital pulse rate ramping circuits

Claim 1

A circuit for digitally supplying pulses to the motor driver of a stepping motor, said stepping motor responding to each pulse with a step as long as its acceleration capability is not exceeded, comprising: a. A source of pulses; b. A reversible counter connected to receive and count the pulses from the source; c. A clock oscillator for supplying a train of pulses at a specific frequency; d. A pulse rate multiplier connected to receive the clock pulse train and multiply the frequency of said pulse train by a factor directly proportional to the count accumulated in the reversible counter; e. A frequency divider connected to receive the modified clock pulse train from the rate multiplier and divide it by a factor suitable to smooth the rate of the modified clock pulse train; f. A pulse generator for supplying a train of pulses at a minimum rate; g. A comparator connected to receive the pulses from the frequency divider and the minimum pulse rate generator and to pass whichever of said pulses has the higher rate; and h. Means to apply the pulses passed by the comparator to the reversible counter to reduce the count therein.