US3885106A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Telephone exchange having permanent memory for operating instructions
Assignee: TELE RESOURCES Inc
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Filing: 1973-07-02
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Granted: 1975-05-20
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Expires: 1993-07-02
Abstract
Abstract A private automatic branch exchange for a telephony system includes a read only memory in which binary coded operating instructions are recorded. Each instruction includes one or more words occupying sequential address positions. An address register reads the instructions from the memory in response to clock pulses. A decoder determines the number of words in the instruction and cause successive words to be loaded into appropriate instruction register positions. Clock pulses are blocked from reaching the address register after an instruction has been read out which requires more than one clock cycle for execution.
Inventors
- 👤 Herman Deutsch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:48
CPC Classifications
G; G04; G04F; G04F10/00; G04F10/04; H; H04; H04J; H04J3/00; H04J3/02; H04J3/04; H04J3/047; H04M; H04M3/00; H04M3/42; H04M3/56; H04M3/561; H04M3/58; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
178 words
A branch exchange for a telephony system comprising a plurality of interconnectable equipments each forming a source of audio signals, temporary memory means for recording equipment addresses and status information relating to each recurring time slot within the system, a read only memory having recorded therein a multiplicity of binary coded words forming instructions for the automatic establishment and disestablishment of time division connections within the system, each instruction including one or more words and all words of each instruction occupying sequential address positions within the memory, a source of clock pulses occurring at predetermined intervals, address register means responsive to said clock pulses for accessing sequential instructions within said memory, data register means for receiving the output of the memory, decoder means for identifying instructions which require more than one clock cycle for execution, clock pulse gating means for blocking clock pulses from reaching the address register, and search frame counter means responsive to the decoder means for activating the clock pulse gatE means for an interval equal in duration to one complete frame of time slots.
Claim 2
Dependent Claim
178 words
A branch exchange for a telephony system comprising a plurality of interconnectable equipments each forming a source of audio signals, temporary memory means for recording equipment addresses and status information relating to each recurring time slot within the system, a read only memory having recorded therein a multiplicity of binary coded words forming instructions for the automatic establishment and disestablishment of time division connections within the system, each instruction including one or more words and all words of each instruction occupying sequential address positions within the memory, a source of clock pulses occurring at predetermined intervals, address register means responsive to said clock pulses for accessing sequential instructions within said memory, data register means for receiving the output of the memory, decoder means for identifying instructions which require more than one clock cycle for execution, clock pulse gating means for blocking clock pulses from reaching the address register, and search frame counter means responsive to the decoder means for activating the clock pulse gatE means for an interval equal in duration to one complete frame of time slots.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1, wherein said read only memory is a metal oxide semiconductor device.
Claim 4
Dependent Claim
34 words
The apparatus of claim 1, further comprising instruction register means for receiving and storing the successive words of multiword instructions from the data register means whereby all words of the instruction are simultaneously presented.
Claim 5
Dependent Claim
28 words
The apparatus of claim 3, further comprising instruction counter means for controlling the portions of the instruction register means into which the words of an instruction are loaded.
Claim 6
Independent Claim
201 words
A method of providing coded operating instructions to control the establishment and disestablishment of time division audio connections between sources of audio signals in an automatic branch exchange for a telephony system comprising: maintaining in a temporary memory a constantly updated record of currently established connections and the addresses of audio signal sources involved in those connections: periodically and continuously supplying clock pulses to an address register and reading permanently recorded instructions from a permanent memory in response to all clock pulses that are not blocked; decoding a portion of the first word of each instruction to determine the number of words in that instruction; setting an instruction register to temporarily record therein the successive words of the instruction; decoding the instruction to determine whether the address register should read the next instruction sequentially or whether it should branch to a designated permanent memory address and controlling the address register accordingly; and further decoding the instruction to determine whether it requires a search of information available within the temporary memory relating to established connections; and blocking clock pulses in response to the decoding of a search instruction and searching the contents of the temporary memory while said clock pulses are blocked.
Claim 7
Independent Claim
201 words
A method of providing coded operating instructions to control the establishment and disestablishment of time division audio connections between sources of audio signals in an automatic branch exchange for a telephony system comprising: maintaining in a temporary memory a constantly updated record of currently established connections and the addresses of audio signal sources involved in those connections: periodically and continuously supplying clock pulses to an address register and reading permanently recorded instructions from a permanent memory in response to all clock pulses that are not blocked; decoding a portion of the first word of each instruction to determine the number of words in that instruction; setting an instruction register to temporarily record therein the successive words of the instruction; decoding the instruction to determine whether the address register should read the next instruction sequentially or whether it should branch to a designated permanent memory address and controlling the address register accordingly; and further decoding the instruction to determine whether it requires a search of information available within the temporary memory relating to established connections; and blocking clock pulses in response to the decoding of a search instruction and searching the contents of the temporary memory while said clock pulses are blocked.
Claim 8
Dependent Claim
23 words
The method of claim 5, wherein clock pulses are blocked for an interval equal in duration to one complete frame of time slots.
Claim 9
Dependent Claim
23 words
The apparatus of claim 1, wherein at least some audio signal sources are hardwired by discrete lines to indicate their class of service.
Claim 10
Dependent Claim
24 words
The apparatus of claim 1, wherein at least some audio signal sources are hardwired by discrete lines to indicate whether they have rotary status.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |