US3885099A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated logic circuit for the decoder of a multi-channel stereo apparatus
Assignee: Sony Corp
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Filing: 1973-11-29
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Granted: 1975-05-20
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Expires: 1993-11-29
Abstract
Abstract A logic circuit which is easily and relatively inexpensively produced as an integrated circuit for use with the decoder of a multi-channel stereo apparatus of the type which converts two composite signals LT and RT into four output signals containing dominant signal components LF'',RF'',LB'', respectively, with each of the output signals further including subdominant signal components as crosstalk. The logic circuit includes a plurality of full wave rectifiers for separately rectifying each of the four output signals, a first differential amplifier for producing a signal representative of the difference between the rectified LF'' and RF'' output signals and a second differential amplifier for producing an output signal representative of the difference between the rectified LB'' and RB'' output signals. The difference signal outputs are compared in a third differential amplifier which generates first and second control signals of opposite polarity which are each representative of the difference between the difference signal outputs. These control signals may be employed to control respective gain control amplifiers interposed in four output signals transmitting lines so as to depress the crosstalk.
Inventors
- 👤 Katsuaki Tsurushima
- 👤 Yoshio Ota
- 👤 Masashi Takeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 04:22
CPC Classifications
H; H04; H04S; H04S3/00; H04S3/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
262 words
In a multi-channel stereo apparatus which has decoder means for decoding two composite signals into at least first, second, third and fourth decoding output signals each containing a dominant signal component and at least one subdominant signal component, logic means for detecting the dominant signal component contained in each of said decoding output signals and producing first and second control signals, and variable transmission means for varying the transmitting conditions for said decoding output signals in response to said control signals; said logic means being in the form of an integrated circuit comprising first, second, third, fourth, fifth, sixth, seventh and eighth transistors each having a base, emitter and collector, said first and second transistors constituting a first differential amplifier, said third and fourth transistors constituting a second different amplifier, means for applying said first, second, third and fourth decoding output signals to the bases of said first, second, third and fourth transistors, respectively, the bases of said fifth, sixth, seventh and eighth transistors being respectively connected to the collectors of said first, second, third and fourth transistors, the collectors of said fifth and sixth transistors being connected to each other and to a first output terminal, the collectors of said seventh and eighth transistors being connected to each other and to a second output terminal, and means for connecting together the emitters of said fifth, sixth, seventh and eighth transistors so that said fifth, sixth, seventh and eighth transistors constitute a third differential amplifier and said first and second control signals are respectively obtained at said first and second output terminals.
Claim 2
Dependent Claim
262 words
In a multi-channel stereo apparatus which has decoder means for decoding two composite signals into at least first, second, third and fourth decoding output signals each containing a dominant signal component and at least one subdominant signal component, logic means for detecting the dominant signal component contained in each of said decoding output signals and producing first and second control signals, and variable transmission means for varying the transmitting conditions for said decoding output signals in response to said control signals; said logic means being in the form of an integrated circuit comprising first, second, third, fourth, fifth, sixth, seventh and eighth transistors each having a base, emitter and collector, said first and second transistors constituting a first differential amplifier, said third and fourth transistors constituting a second different amplifier, means for applying said first, second, third and fourth decoding output signals to the bases of said first, second, third and fourth transistors, respectively, the bases of said fifth, sixth, seventh and eighth transistors being respectively connected to the collectors of said first, second, third and fourth transistors, the collectors of said fifth and sixth transistors being connected to each other and to a first output terminal, the collectors of said seventh and eighth transistors being connected to each other and to a second output terminal, and means for connecting together the emitters of said fifth, sixth, seventh and eighth transistors so that said fifth, sixth, seventh and eighth transistors constitute a third differential amplifier and said first and second control signals are respectively obtained at said first and second output terminals.
Claim 3
Dependent Claim
67 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 1; further comprising first and second slice means connected to said first and second differential amplifiers, respectively, so that the transistors of the respective differential amplifier are turned ON only when the differences between the first and second decoding output signals and between the third and fourth decoding output signals exceed a predetermined value.
Claim 4
Dependent Claim
121 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 2; in which each of said first and second slice means includes first and second transistors, and a constant current source connected to the base of said first and second transistors of the respective slice means; and in which the emitters and collectors of said first and second transistors of said first slice means are connected to the emitters and collectors of said first and second transistors, respectively, of said first differential amplifier, and the emitters and collectors of said first and second transistors of said second slice means are connected to the emitters and collectors of said third and fourth transistors, respectively, of the second differential amplifier.
Claim 5
Dependent Claim
25 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 3; further comprising third slice means connected with said third differential amplifier.
Claim 6
Dependent Claim
94 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 4; in which said third slice means includes first and second transistors each having a base, emitter and collector, the bases of said first and second transistors of said third slice means are connected to each other and receive a predetermined bias voltage, and the collectors and emitters of said first and second transistors of the third slice means are connected with the collectors and emitters, respectively, of said fifth and sixth transistors and of said seventh and eighth transistors, respectively.
Claim 7
Dependent Claim
24 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 1; further comprising slice means connected with said third differential amplifier.
Claim 8
Dependent Claim
91 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 6; in which said slice means includes first and second transistors each having a base, emitter and collector, the bases of said first and second transistors of the slice means are connected to each other and receive a predetermined bias voltage, and the collectors and emitters of said first and second transistors of the slice means are connected with the collectors and emitters, respectively, of said fifth and sixth transistors and of said seventh and eight transistors, respectively.
Claim 9
Dependent Claim
50 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 1; in which time constant circuits are connected with the bases of said first and second transistors constituting said first differential amplifier and with the bases of said third and fourth transistors constituting the second differential amplifier.
Claim 10
Dependent Claim
75 words
In a multi-channel stereo apparatus, an integrated circuit logic means as in claim 8; in which the time constant circuits include resistors respectively interposed in said means for applying the first, second, third and fourth decoding output signals to the bases of said first, second, third and fourth transistors, aNd capacitors respectively interposed between terminals connected to the bases of said first and second transistors and between terminals connected to said third and fourth transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-19 | 1978-11-18 | 1979-05-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-19 | 1982-11-18 | 1983-05-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-19 | 1986-11-18 | 1987-05-20 | $7700.00 | Window Closed / Lapsed |