System for phase aligning parallel signal processing channels

Claim 1

A system for automatically phase aligning two signal processing channels of the type which includes a mixer for frequency translation and a local oscillator coupled to the mixer in each processing channel; said system comprising: test generator means for applying test signals, having a preselected phase relationship, to the input section of each processing channel; phase detector means coupled to the output section of each said processing channel for providing a binary phase sense signal indicative of whether the phase between the channels'' output signals is more or less than a preselected value; a digitally controllable phase shifter coupled between the local oscillator and the mixer of one of said signal processing channels; and control means coupled to said phase shifter and responsive to said phase sense signal, for controlling the phase shift of the local oscillator''s output signal applied through said phase shifter so as to cause a preselected phase relationship between the output signals from said two processing channels; said control means including an up/down counter, first logic means for causing said counter to count up when said binary phase sense signal is of one state and to count down when said binary phase sense signal is of the other state, and second logic means for sensing the change of states of said binary phase sense signal and for inhibiting counting by said up/down counter after a preselected number of said binary signal state changes have been sensed; and means for applying the output signals from said up/down counter to said phase shifter so that the phase shift applied to the local oscillator''s output signal by said phase shifter is controlled as a function of the count held in said up/down counter.

Claim 2

A system for automatically phase aligning two signal processing channels of the type which includes a mixer for frequency translation and a local oscillator coupled to the mixer in each processing channel; said system comprising: test generator means for applying test signals, having a preselected phase relationship, to the input section of each processing channel; phase detector means coupled to the output section of each said processing channel for providing a binary phase sense signal indicative of whether the phase between the channels'' output signals is more or less than a preselected value; a digitally controllable phase shifter coupled between the local oscillator and the mixer of one of said signal processing channels; and control means coupled to said phase shifter and responsive to said phase sense signal, for controlling the phase shift of the local oscillator''s output signal applied through said phase shifter so as to cause a preselected phase relationship between the output signals from said two processing channels; said control means including an up/down counter, first logic means for causing said counter to count up when said binary phase sense signal is of one state and to count down when said binary phase sense signal is of the other state, and second logic means for sensing the change of states of said binary phase sense signal and for inhibiting counting by said up/down counter after a preselected number of said binary signal state changes have been sensed; and means for applying the output signals from said up/down counter to said phase shifter so that the phase shift applied to the local oscillator''s output signal by said phase shifter is controlled as a function of the count held in said up/down counter.

Claim 4

A system for automatically phase aligning parallel signal processing channels of the type used in the antenna-receiver subassembly of monopulse radars wherein each channel includes a mixer operatively coupled to a source of local oscillator signals so that signals applied through the processing channels are translated in frequency, said system comprising: test generator means for applying test signals to the input sections of said processing channels such that there is a preselected phase between the applied test signals; a digitally controllable phase shifter coupled in series with the local oscillator signal applied to the mixer in one of said processing channels; phase detector means coupled to the output section of each said processing channel for providing a binary phase sense signal indicative of whether the phase between the channels'' output signals is more or less than a preselected value; control means coupled between said phase detector means and said digitally controllable phase shifter for controlling the phase shifter as a function of said binary phase sense signal, said control means including an up/down counter, first logic means for causing said counter to count up when said binary phase sense signal is of one state and to count down when said binary phase sense signal is of the other state, and second logic means for sensing the change of states of said binary phase sense signal and for inhibiting counting of said up/down counter after a preselected number of said binary signal state changes has been sensed, and means for applying the output signals from said up/down counter to said digital phase shifter so that the phase shift applied to the local oscillator''s output signal by said digital phase shifter, is controlled as a function of the count of said up/down counter.

Claim 5

A system for automatically phase aligning parallel signal processing channels of the type used in the antenna-receiver subassembly of monopulse radars wherein each channel includes a mixer operatively coupled to a source of local oscillator signals so that signals applied through the processing channels are translated in frequency, said system comprising: test generator means for applying test signals to the input sections of said processing channels such that there is a preselected phase between the applied test signals; a digitally controllable phase shifter coupled in series with the local oscillator signal applied to the mixer in one of said processing channels; phase detector means coupled to the output section of each said processing channel for providing a binary phase sense signal indicative of whether the phase between the channels'' output signals is more or less than a preselected value; control means coupled between said phase detector means and said digitally controllable phase shifter for controlling the phase shifter as a function of said binary phase sense signal, said control means including an up/down counter, first logic means for causing said counter to count up when said binary phase sense signal is of one state and to count down when said binary phase sense signal is of the other state, and second logic means for sensing the change of states of said binary phase sense signal and for inhibiting counting of said up/down counter after a preselected number of said binary signal state changes has been sensed, and means for applying the output signals from said up/down counter to said digital phase shifter so that the phase shift applied to the local oscillator''s output signal by said digital phase shifter, is controlled as a function of the count of said up/down counter.