US3883791A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Three phase sequence insensitive full range SCR firing circuit
Assignee: Cooper Industries LLC
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Filing: 1974-03-15
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Granted: 1975-05-13
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Expires: 1994-03-15
Abstract
Abstract A three phase SCR firing circuit for a DC power supply is disclosed herein. The firing circuit is not effected by the sequence in which the three power lines are connected to the firing circuit and the circuit fully controls the output of the SCRs over the full range of power output of the SCRs.
Inventors
- 👤 William B Zelina
- 👤 Joseph M Allison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:24
CPC Classifications
H; H02; H02M; H02M7/00; H02M7/02; H02M7/04; H02M7/12; H02M7/145; H02M7/155; H02M7/162; H02M7/1623
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
123 words
A three phase, sequence insensitive, full range SCR firing circuit comprising a three phase power supply comprising three SCRs each having anodes, cathodes, and gates, the cathodes of said SCRs being connected to an output line, power lines connected to said anodes, gating means connected to said gates, a tri-state memory means connected to said gating means, said tri-state memory being adapted to follow said power supply phase sequence, and a modulator means connected to said tri-state memory means for generating the pulse for said gating means, said tri-state memory means being adapted to steer said pulse from said modulator means to said gates of said SCRs whereby the output of said SCRs is controlled over substantially a full range of power output.
Claim 2
Dependent Claim
123 words
A three phase, sequence insensitive, full range SCR firing circuit comprising a three phase power supply comprising three SCRs each having anodes, cathodes, and gates, the cathodes of said SCRs being connected to an output line, power lines connected to said anodes, gating means connected to said gates, a tri-state memory means connected to said gating means, said tri-state memory being adapted to follow said power supply phase sequence, and a modulator means connected to said tri-state memory means for generating the pulse for said gating means, said tri-state memory means being adapted to steer said pulse from said modulator means to said gates of said SCRs whereby the output of said SCRs is controlled over substantially a full range of power output.
Claim 3
Dependent Claim
19 words
The circuit recited in claim 1 wherein said tri-state memory means comprises a plurality of AND and NOR circuits.
Claim 4
Dependent Claim
24 words
The circuit recited in claim 1 Wherein a voltage reference means for sensing load voltage is connected from said output line to said modulator.
Claim 5
Dependent Claim
39 words
The circuit recited in claim 3 wherein a voltage reference is provided, said voltage reference is connected to a first comparator, said first comparator is connected to said modulator, whereby said modulator is provided with a load voltage reference.
Claim 6
Dependent Claim
49 words
The circuit recited in claim 1 wherein a load means is connected to said circuit and a current reference means is connected to load means, and a second comparator is connected to said current reference and to said modulator, whereby said modulator is provided with a load current reference.
Claim 7
Dependent Claim
59 words
The circuit recited in claim 1 wherein said circuit includes four separate phase reference means, said reference means being connected to said modulator, said modulator having means whereby a signal from one of said reference means takes priority over the signals from the other said reference means depending on the range of the firing angle of said reference signals.
Claim 8
Dependent Claim
64 words
The circuit recited in claim 1 wherein said tri-state memory means has memory inputs having tru/false logic values that depend on the magnitudes and/or polarities of said three phase line voltages or the magnitudes and/or polarities of the voltages across said SCRs, said memory being constructed such that time sequencing of the memory output states follows the phase sequence of said power line voltages.
Claim 9
Dependent Claim
27 words
The circuit recited in claim 7 wherein before said memory means is connected to said modulator an providing 150% modulation of the voltage put into said modulator.
Claim 10
Dependent Claim
27 words
The circuit recited in claim 1 wherein said modulator means is a single modulator having four separate inputs connected to four separate input means in said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-12 | 1978-11-11 | 1979-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-12 | 1982-11-11 | 1983-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-12 | 1986-11-11 | 1987-05-13 | $7700.00 | Window Closed / Lapsed |