Phase locked loop transmitter

Claim 2

A phase locked loop transmitter comprising: a first source of modulated input signals; a second source of stabilized reference signals having a given frequency; a mixer coupled to said first and second sources; a phase locked loop including a phase detector having two inputs, one of said two inputs of said phase detector being coupled to the output of said mixer, a loop amplifier coupled to the output of said phase detector, a voltage controlled oscillator having its frequency control input coupled to the output of said loop amplifier providing an output signal having a frequency equal to a submultiple of said given frequency, a directional coupler coupled to the output of said controlled oscillator, a low power frequency multiplier coupled to one output of said directional coupler to provide an output signal having a frequency equal to said given frequency, a bandpass filter coupled to the output of said low power frequency multiplier, a phase shifter coupled to the output of said bandpass filter, and a variable attenuator coupled between the output of said phase shifter and the other of said two inputs of said phase detector; a power amplifier coupled to the other output of said directional coupler; and a high power frequency multiplier coupled to the output of said power amplifier to provide an output signal having said given frequency for said transmitter.

Claim 3

A transmitter according to claim 1, wherein said loop amplifier includes a differential amplifier.

Claim 4

A transmitter according to claim 2, wherein said phase detector includes a 90* 3 decibel hybrid coupler having two outputs and two inputs, one of said two inputs of said coupler being coupled to said mixer and the other of said two inputs of said coupler being coupled to said attenuator, a capacitance coupling and matching network coupled to each of said two outputs, a diode coupled to each of said networks, and a balancing potentiometer having a slider coupled to the input of said differential amplifier, one terminal connected to one of said diodes and the other terminal connected to the other of said diodes.

Claim 5

A transmitter according to claim 2, wherein said differential amplifier includes two stages, each of said two stages having a first NPN transistor having a collector, an emitter and a base coupled to the output of said phase detector, ground potential, a first resistor coupled between said collector of said first transistor and said ground potential, a second resistor coupled between said base and said collector of said first transistor, a second NPN transistor having a collector, an emitter and a base coupled to said collector of said first transistor, a third resistor coupled between said collector of said second transistor and said ground potential, said collector of said second transistor being coupldd to said frequency control input of said controlled oscillator, a feedback network including a fourth resistor connected in series with a first capacitor, said feedback network being connected between said collector of said second transistor and said emitter of said first transistor, a negative biaS potential, a fifth resistor coupled to said negative bias potential, a second capacitor coupled in shunt relation with a sixth resistor, said second capacitor and said sixth resistor being connected between said emitter of said first transistor and said fifth resistor, a seventh resistor coupled between said negative bias potential and said emitter of said second transistor, an eighth resistor coupled to said base of said first transistor, a third capacitor coupled to said ground potential, a ninth resistor coupled between said eighth resistor and said third capacitor, a clamp circuit including the series connected of a tenth resistor and a diode, said clamp circuit being coupled between said negative bias potential and the junction of said eighth and ninth resistors, and a fourth capacitor being coupled between said ground potential and the junction of said fifth resistor and the shunt combination of said second capacitor and said sixth resistor.

Claim 6

A transmitter according to claim 4, wherein said phase detector includes a 90* 3 decibel hybrid coupler having two outputs and two inputs, one of said two inputs of said coupler being coupled to said mixer and the other of said two inputs of said coupler being coupled to said attenuator, a capacitance coupling and matching network coupled to each of said two outputs, a diode coupled to each of said networks and a balancing potentiometer having a slider coupled to said base of said first transistor, one terminal connected to one of said diodes and the other terminal connected to the other of said diodes.

Claim 7

A transmitter according to claim 1, wherein said loop amplifier includes two stages, each of said two stages having a first NPN transistor having a collector, an emitter and a base coupled to the output of said phase detector, ground potential, a first resistor coupled between said collector of said first transitor and said ground potential, a second transistor coupled between said base and said collector of said first transistor, a second NPN transistor having a collector, an emitter and a base coupled to said collector of said first transistor, a third resistor coupled between said collector of said second transistor and said ground potential, said collector of said second transistor being coupled to said frequency control input of said controlled oscillator, a feedback network including a fourth resistor connected in series with a first capacitor, said feedback network being connected between said collector of said second transistor and said emitter of said first transistor, a negative bias potential, fifth resistor coupled to said negative bias potential, a second capacitor coupled in shunt relation with a sixth resistor, said second capacitor and said sixth resistor being connected between said emitter of said first transistor and said fifth resistor, a seventh resistor coupled between said negative bias potential and said emitter of said second transistor, an eighth resistor coupled to said base of said first trnasistor, a third capacitor to said ground potential, a ninth resistor coupled between said eighth resistor and said third capacitor, a clamp circuit including the series connection of a tenth resistor and a diode, said clamp circuit being coupled between said negative bias potential and the junction of said eighth and ninth resistors, and a fourth capacitor being coupled between said ground potential and the junction of said fifth resistor and the shunt combination of said second capacitor and said sixth resistor.

Claim 8

A transmitter according to claim 1, wherein said phase detector includes a 90* 3 decibel hydrid coupler having two outputs and two inputs, one of said two inputs of said coupler being coupled to said mixer and the other of said two inputs of said coupler being coupled to said attenuator, a capacitAnce coupling and matching network coupled to each of said two outputs, a diode coupled to each of said networks, and a balancing potentiometer having a slider coupled to said loop amplifier, one terminal connected to one of said diodes and the other terminal connected to the other of said diodes.

Claim 9

A transmitter according to claim 1, wherein said loop amplifier includes two stages, each of said two stages having a first NPN transistor having a collector, an emitter and a base coupled to the output of said phase detector, ground potential, a first resistor coupled between said collector of said first transistor and said ground potential, a second resistor coupled between said base and said collector of said first transistor, a second NPN transistor having a collector, an emitter and a base coupled to said collector of said first transistor, a third resistor coupled between said collector of said second transistor and said ground potential, said collector of said second transistor being coupled to said frequency control input of said controlled oscillator, a feedback network including a fourth resistor connected in series with a first capacitor, said feedback network being connected between said collector of said second transistor and said emitter of said first transistor, a negative bias potential, a fifth resistor coupled to said negative bias potential, a second capacitor coupled in shunt relation with a sixth resistor, said second capacitor and said sixth resistor being connected between said emitter of said first transistor and said fifth resistor, a seventh resistor coupled between said negative bias potential and said emitter of said second transistor, an eighth resistor coupled to said base of said first transistor, a third capacitor coupled to said ground potential, a ninth resistor coupled between said eighth resistor and said third capacitor, a clamp circuit including the series connection of a tenth resistor and a diode, said clamp circuit being coupled between said negative bias potential and the junction of said eighth and ninth resistors, and a fourth capacitor being coupled between said ground potential and the junction of said fifth resistor and the shunt combination of said second capacitor and said sixth resistor; and said phase detector includes a 90* 3 decibel hybrid coupler having two outputs and two inputs, one of said two inputs of said coupler being coupled to said mixer and the other of said two inputs of said coupler being coupled to said attenuator, a capacitance coupling and matching network coupled to each of said two outputs, a diode coupled to each of said networks, and a balancing potentiometer having a slider coupled to said base of said first transistor, one terminal connected to one of said diodes and the other terminal connected to the other of said diodes.