US3882390A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flip-flop balance testing circuit
Assignee: AT&T Inc
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Filing: 1974-07-31
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Granted: 1975-05-06
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Expires: 1994-07-31
Abstract
Abstract A testing circuit for determining the probability of a crosscoupled flip-flop existing in a balanced state within a predetermined input timing range as the result of critically timed input signals. One of the inputs of the flip-flop under test has applied thereto periodic input signals while the other input has applied input signals the timing of which is caused to vary around the timing of the other input signals. Within this latter timing range, at the perfect ''''race'''' point, i.e., when both inputs precisely coincide in time, the flip-flop will be balanced to generate two equal voltage levels somewhere between a logic ''''1'''' and ''''0.'''' The number of balances are counted at a specified balance duration together with the number of trials over the predetermined timing range to achieve sums for computing balance probability at the duration of balance specified.
Inventors
- 👤 James Allen Lucas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:46
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318522; G01R31/318525
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
118 words
An electrical flip-flop balance testing circuit comprising first circuit means for applying a plurality of first input signals to one input of a flip-flop under test at periodic points in time, second circuit means for applying a plurality of second input signals to the other input of said flip-flop at times continuously varying around said periodic points in time, detector circuit means for generating balance signals responsive to equal output signals on the outputs of said flip-flop, first counter circuit means for counting said balance signals during a predetermined time interval for generating a balance sum signal, and second counter means for counting said first input signals during said predetermined time interval for generating an attempt sum signal.
Claim 2
Dependent Claim
118 words
An electrical flip-flop balance testing circuit comprising first circuit means for applying a plurality of first input signals to one input of a flip-flop under test at periodic points in time, second circuit means for applying a plurality of second input signals to the other input of said flip-flop at times continuously varying around said periodic points in time, detector circuit means for generating balance signals responsive to equal output signals on the outputs of said flip-flop, first counter circuit means for counting said balance signals during a predetermined time interval for generating a balance sum signal, and second counter means for counting said first input signals during said predetermined time interval for generating an attempt sum signal.
Claim 3
Dependent Claim
32 words
An electrical flip-flop balance testing circuit as claimed in claim 1 also comprising circuit means for combining said balance sum signal and said atempt sum signal for generating a balance probability signal.
Claim 4
Dependent Claim
70 words
An electrical flip-flop balance testing circuit as claimed in claim 2 in which said second circuit means comprises a comparator circuit having a pair of inputs, first signal generating means for applying a low frequency sawtooth waveform to one of said comparator inputs, and second signal generating means for applying periodic pulses having finite rise and fall times and of a high frequency to the other of said comparator inputs.
Claim 5
Dependent Claim
166 words
An electrical test circuit comprising a first and a second pair of terminals adapted to have a pair of inputs and a pair of outputs, respectively, of an electrical flip-flop circuit connected thereto, a first signal source for applying a plurality of first pulses to one terminal of said first pair of terminals at periodic points in time, a second signal source for applying a plurality of second pulses to the other terminal of said first pair of terminals at times coinciding with, and continually varying about, said periodic points in time, a balance detector circuit means for generating balance signals responsive to substantially equal potential conditions on said second pair of terminals, first counter circuit means for counting said first pulses and for generating first data representative of the sum of said first pulses during a predetermined interval, and second counter circuit means for counting said balance signals and for generating second data representative of the sum of said balance signals during said predetermined interval.
Claim 6
Dependent Claim
166 words
An electrical test circuit comprising a first and a second pair of terminals adapted to have a pair of inputs and a pair of outputs, respectively, of an electrical flip-flop circuit connected thereto, a first signal source for applying a plurality of first pulses to one terminal of said first pair of terminals at periodic points in time, a second signal source for applying a plurality of second pulses to the other terminal of said first pair of terminals at times coinciding with, and continually varying about, said periodic points in time, a balance detector circuit means for generating balance signals responsive to substantially equal potential conditions on said second pair of terminals, first counter circuit means for counting said first pulses and for generating first data representative of the sum of said first pulses during a predetermined interval, and second counter circuit means for counting said balance signals and for generating second data representative of the sum of said balance signals during said predetermined interval.
Claim 7
Dependent Claim
55 words
An electrical test circuit as claimed in claim 4 in which said second signal source comprises a comparator circuit having a first and a second input, said first comparator input also having said plurality of first pulses applied thereto, and a signal generating means for applying a substantially sawtooth waveform to said second comparator input.
Claim 8
Dependent Claim
37 words
An electrical test circuit as claimed in claim 5 in which the frequency of said sawtooth waveform is in the one hertz range and the frequency of said plurality of second pulses is in the megahertz range.
Claim 9
Dependent Claim
43 words
An electrical test circuit as claimed in claim 5 also comprising circuit means for combining said first data and said second data for generating output data representing the quotient of said sum of said first pulses and said sum of said balance signals.
Claim 10
Dependent Claim
25 words
An electrical test circuit as claimed in claim 7 also comprising visual display means operated responsive to said output data for visually presenting said quotient.
Claim 11
Dependent Claim
109 words
A circuit for testing the balance operating conditions of a flip-flop having a pair of inputs and a pair of outputs comprising a sawtooth generator for generating a series of pulses at a firsT frequency, a pulse generator for generating pulses at a substantially higher frequency, a comparator circuit connected to the outputs of both said sawtooth generator and said pulse generator for applying control signals to one of said flip-flop inputs, a delay circuit connected to said pulse generator for applying control signals to the other of said flip-flop inputs, and balance detector circuitry connected to both of the outputs of said flip-flop for generating flip-flop balance signals.
Claim 12
Dependent Claim
109 words
A circuit for testing the balance operating conditions of a flip-flop having a pair of inputs and a pair of outputs comprising a sawtooth generator for generating a series of pulses at a firsT frequency, a pulse generator for generating pulses at a substantially higher frequency, a comparator circuit connected to the outputs of both said sawtooth generator and said pulse generator for applying control signals to one of said flip-flop inputs, a delay circuit connected to said pulse generator for applying control signals to the other of said flip-flop inputs, and balance detector circuitry connected to both of the outputs of said flip-flop for generating flip-flop balance signals.
Claim 13
Dependent Claim
33 words
A circuit for testing the balance operating conditions of a flip-flop as claimed in claim 9 also comprising a first counter circuit means for counting said balance signals for generating sum balance data.
Claim 14
Dependent Claim
37 words
A circuit for testing the balance operating conditions of a flip-flop as claimed in claim 10 also comprising a second counter circuit means for counting said pulses generated by said pulse generator for generating sum attempts data.
Claim 15
Dependent Claim
44 words
A circuit for testing the balance operating conditions of a flip-flop as claimed in claim 11 also comprising means for combining said sum balance data and said sum attempts data for generating output signals representing the quotient of said sum balance and attempts data.
Claim 16
Dependent Claim
30 words
A circuit for testing the balance operating conditions of a flip-flop as claimed in claim 12 also comprising means operated responsive to said output signals for perceptibly presenting said quotient.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-05 | 1978-11-04 | 1979-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-05 | 1982-11-04 | 1983-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-05 | 1986-11-04 | 1987-05-06 | $7700.00 | Window Closed / Lapsed |