US3881065A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for aligning data envelope formats to PCM word formats
Assignee: QUEFFEULOU JEAN YVES
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Filing: 1974-03-07
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Granted: 1975-04-29
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Expires: 1994-03-07
Abstract
Abstract A facility for restoring the phase of data envelopes having a number m of bits and starting with an envelope framing bit, the envelopes forming a flow of bits including transmitted envelope framing bits and being passed through a time-division switching network designed to switch n-bit PCM words located in the time slots of consecutive frames of a time division switching network wherein, m being greater than n. It comprises means for serially receiving the flow of bits formed by the envelopes and means for generating a multiframe signal having a length equal to a whole number of envelopes and to a whole number of frames, composed of local envelope framing bits distributed from m to m in the length of the multiframe signal. The transmitted envelope framing bits contained in the flow of bits and the local envelope framing bits are compared in a synchronization search device which steps on and delays by one bit interval the transmitted framing bits with respect to the local framing bits as long as synchronism is not achieved. Extra delays of multiples of (m-n) bit intervals are selectively applied to the flow of bits for taking account of the frame jumps due to the passage of the words through the switching network.
Inventors
- 👤 Jean-Yves Queffeulou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:49
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629; H04L; H04L25/00; H04L25/02; H04L25/05; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
243 words
A device for phasing up data envelopes containing a number m of bits and starting with an envelope framing bit, the envelopes forming a flow of bits including transmitted envelope framing bits and being passed through a time division switching network adapted to switch n-bit PCM words transmitted in time slots of the consecutive frames of said time division switching network, the number m of bits per envelope being greater than the number n of bits per word and said switching network applying to some of said PCM words a transmission delay equal to an integer number of frames nf, said device comprising means for serially receiving the flow of bits, means for selectively delaying said flow of bits by delays equal to intervals of 1, 2, . . . (m-1) bits, means for generating a multiframe signal of a length equal to whole numbers of frames and of envelopes, composed of local envelope framing bits distributed from m to m in the length of the multiframe signal, means for comparing the flow of bits containing the transmitted envelope framing bits to the local envelope framing bits; means controlled by said comparing means for varying the delay of saId delaying means, means for storing the integer number nf of frames forming the delay experienced by the PCM words passing through the switching network, and means for applying to the flow of bits an extra delay equal to (m-n) X nf intervals of bits.
Claim 2
Independent Claim
243 words
A device for phasing up data envelopes containing a number m of bits and starting with an envelope framing bit, the envelopes forming a flow of bits including transmitted envelope framing bits and being passed through a time division switching network adapted to switch n-bit PCM words transmitted in time slots of the consecutive frames of said time division switching network, the number m of bits per envelope being greater than the number n of bits per word and said switching network applying to some of said PCM words a transmission delay equal to an integer number of frames nf, said device comprising means for serially receiving the flow of bits, means for selectively delaying said flow of bits by delays equal to intervals of 1, 2, . . . (m-1) bits, means for generating a multiframe signal of a length equal to whole numbers of frames and of envelopes, composed of local envelope framing bits distributed from m to m in the length of the multiframe signal, means for comparing the flow of bits containing the transmitted envelope framing bits to the local envelope framing bits; means controlled by said comparing means for varying the delay of saId delaying means, means for storing the integer number nf of frames forming the delay experienced by the PCM words passing through the switching network, and means for applying to the flow of bits an extra delay equal to (m-n) X nf intervals of bits.
Claim 3
Dependent Claim
72 words
A device for phasing up data envelopes as claimed in claim 1 wherein the means for serially receiving the flow of bits and the means for selectively delaying the same consist of a shift register having a single serial input and m serial outputs exhibiting with respect to said input delays equal to 0, 1, 2, . . . (m-1) bit intervals and of means for selecting one of said outputs respectively.
Claim 4
Independent Claim
287 words
A device for phasing up data envelopes containing a number m of bits and starting with an envelope framing bit, the envelopes forming a flow of bits including transmitted envelope framing bits and being passed through a time division switching network adapted to switch n-bit PCM words transmitted in time slots of the consecutive frames of said time division switching network, the number m of bits per envelope being greater the the number n of bits per word and said switching network applying to some of said PCM words a transmission delay equal to an integer number of frames nf, said device comprising a m-stage shift register having one serial input and m serial outputs, the outgoing flow of bits through respective ones of said outputs exhibiting a delay of 0, 1, 2, . . . (m-1) bit intervals with respect to the incoming flow of bits applied to said input, an address register means for selecting one of said register outputs, means for generating a multiframe signal of a length equal to whole numbers of frames and of envelopes, composed of local envelope framing bits distributed from m to m in the length of the multiframe signal, means for comparing the flow of bits containing the transmitted envelope framing bits to the local envelope framing bits, means controlled by said comparing means for actuating said address register means, means for storing the integer number nf of frames forming the delay experienced by the PCM words passing through the switching network and a plurality of delay means connected to said selected shift register output, controlled by said storing means and applying to the flow of bits an extra delay equal to (m-n) X nf intervals of bits.
Claim 5
Independent Claim
287 words
A device for phasing up data envelopes containing a number m of bits and starting with an envelope framing bit, the envelopes forming a flow of bits including transmitted envelope framing bits and being passed through a time division switching network adapted to switch n-bit PCM words transmitted in time slots of the consecutive frames of said time division switching network, the number m of bits per envelope being greater the the number n of bits per word and said switching network applying to some of said PCM words a transmission delay equal to an integer number of frames nf, said device comprising a m-stage shift register having one serial input and m serial outputs, the outgoing flow of bits through respective ones of said outputs exhibiting a delay of 0, 1, 2, . . . (m-1) bit intervals with respect to the incoming flow of bits applied to said input, an address register means for selecting one of said register outputs, means for generating a multiframe signal of a length equal to whole numbers of frames and of envelopes, composed of local envelope framing bits distributed from m to m in the length of the multiframe signal, means for comparing the flow of bits containing the transmitted envelope framing bits to the local envelope framing bits, means controlled by said comparing means for actuating said address register means, means for storing the integer number nf of frames forming the delay experienced by the PCM words passing through the switching network and a plurality of delay means connected to said selected shift register output, controlled by said storing means and applying to the flow of bits an extra delay equal to (m-n) X nf intervals of bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-28 | 1978-10-28 | 1979-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-28 | 1982-10-28 | 1983-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-28 | 1986-10-28 | 1987-04-29 | $7700.00 | Window Closed / Lapsed |