US3879576A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronizing signal separating circuit
Assignee: Sony Corp
•
Filing: 1973-04-02
•
Granted: 1975-04-22
•
Expires: 1993-04-02
Abstract
Abstract In a synchronizing signal separating circuit comprising an amplifier circuit receiving a composite signal, for example, a video signal, and a self-biasing circuit that includes a capacitor which is charged during each synchronizing signal period of the composite signal and then discharged during the subsequent information signal period; a constant current circuit is provided for discharging of the capacitor so that the separated synchronizing signals obtained as the output of the amplifier circuit will have a uniform pulse width irrespective of the amplitudes of the intervening information signals.
Inventors
- 👤 Takashi Okada
- 👤 Hirouyki Sumiya
- 👤 Tomoyoshi Imayasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:32
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/04; H04N5/08
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
178 words
A circuit for separating synchronizing signals from a composite signal which further includes information signals interposed between successive synchronizing signals, comprising an amplifying transistor receiving said composite signal, selfbiasing means including a capacitor for applying a self-bias to said amplifying transistor in response to said composite signal so that said amplifying transistor is rendered conductive only upon said synchronizing signals in said composite signal, constant current circuit means connected with said self-biasing means for maintaining said self-bias at a substantially constant value at the conclusion of each of said information signals irrespective of the value of the latter, a load resistor connected to said amplifying transistor, means for supplying an operating voltage to said amplifying transistor through said load resistor, bias regulating means connected in series with said load resistor and differential amplifier means having a first input coupled to said load resistor and a second input coupled to said bias regulating means for deriving at the output of said differential amplifier means separated synchronizing signal pulses in correspondence with said synchronizing signal in the received composite signal.
Claim 2
Dependent Claim
178 words
A circuit for separating synchronizing signals from a composite signal which further includes information signals interposed between successive synchronizing signals, comprising an amplifying transistor receiving said composite signal, selfbiasing means including a capacitor for applying a self-bias to said amplifying transistor in response to said composite signal so that said amplifying transistor is rendered conductive only upon said synchronizing signals in said composite signal, constant current circuit means connected with said self-biasing means for maintaining said self-bias at a substantially constant value at the conclusion of each of said information signals irrespective of the value of the latter, a load resistor connected to said amplifying transistor, means for supplying an operating voltage to said amplifying transistor through said load resistor, bias regulating means connected in series with said load resistor and differential amplifier means having a first input coupled to said load resistor and a second input coupled to said bias regulating means for deriving at the output of said differential amplifier means separated synchronizing signal pulses in correspondence with said synchronizing signal in the received composite signal.
Claim 3
Dependent Claim
178 words
A circuit for separating synchronizing signals from a composite signal which further includes information signals interposed between successive synchronizing signals, comprising an amplifying transistor receiving said composite signal, self-biasing means including a capacitor for applying a self-bias to said amplifying transistor in response to said composite signal so that said amplifying transistor is rendered conductive only upon said synchronizing signals in said composite signal, constant current circuit means connected with said self-biasing means for maintaining said self-bias at a substantially constant value at the conclusion of each of said information signals irrespective of the value of the latter, a load resistor connected to said amplifying transistor, means for supplying an operating voltage to said amplifying transistor through said load resistor, bias regulating means connected in series with said load resistor and differential amplifier means having a first input coupled to said load resistor and a second input coupled to said bias regulating means for deriving at the output of said differential amplifier means separated synchronizing signal pulses in correspondence with said synchronizing signal in the received composite signal.
Claim 4
Dependent Claim
178 words
A circuit for separating synchronizing signals from a composite signal which further includes information signals interposed between successive synchronizing signals, comprising an amplifying transistor receiving said composite signal, self-biasing means including a capacitor for applying a self-bias to said amplifying transistor in response to said composite signal so that said amplifying transistor is rendered conductive only upon said synchronizing signals in said composite signal, constant current circuit means connected with said self-biasing means for maintaining said self-bias at a substantially constant value at the conclusion of each of said information signals irrespective of the value of the latter, a load resistor connected to said amplifying transistor, means for supplying an operating voltage to said amplifying transistor through said load resistor, bias regulating means connected in series with said load resistor and differential amplifier means having a first input coupled to said load resistor and a second input coupled to said bias regulating means for deriving at the output of said differential amplifier means separated synchronizing signal pulses in correspondence with said synchronizing signal in the received composite signal.
Claim 5
Dependent Claim
52 words
A circuit in accordance with claim 1 wherein said bias regulating means comprises a regulating transistor having its collector-emitter junction connected in series with said load resistor and further comprising a source of constant potential and means for coupling said source of constant potential to the base electrode of said regulating transistor.
Claim 6
Dependent Claim
53 words
A circuit in accordance with claim 2 wherein said self-biasing means is coupled to the emitter electrode of said amplifying transistor, said constant current circuit means is connected to said emitter electrode of said amplifying transistor and said source of constant potential is additionally connected to the base electrode of said amplifying transistor.
Claim 7
Dependent Claim
62 words
A circuit in accordance with claim 3 wherein said constant current circuit means comprises a first transistor having its collector-emitter junction connected in series between said emitter electrode of said amplifying transistor and a reference potential, and a second transistor connected to the base electrode of said first transistor and disposed in diode-connected configuration and being further supplied with an operating voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-21 | 1978-10-21 | 1979-04-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-21 | 1982-10-21 | 1983-04-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-21 | 1986-10-21 | 1987-04-22 | $7700.00 | Window Closed / Lapsed |