US3878552A
Expired / Lapsed
US
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Bipolar integrated circuit and method
Assignee: Individual
•
Filing: 1972-11-13
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Granted: 1975-04-15
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Expires: 1992-11-13
Abstract
Abstract An integrated circuit formed from starting material including a highly doped substrate of one conductivity type having crystallographic planes at one face thereof which etch preferentially, such as the <100> or <110> planes, and three layers of semiconductor material on said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped buried layer and another layer all of opposite conductivity type with a V-groove extending through said layers and into said substrate to define an island and a well within said island extending to a point adjacent said highly doped buried layer and a diffusion region formed in said well to provide connection to the buried layer together with additional regions formed in said island to define with said layers a bipolar semiconductor device.
Inventors
- 👤 Thurman J Rodgers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:36
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/104; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/20; Y; Y10; Y10S; Y10S148/00; Y10S148/007; Y10S148/025; Y10S148/051; Y10S148/085; Y10S148/115; Y10S148/138; Y10S148/139; Y10S148/168
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
167 words
An integrated circuit including a bipolar semiconductor device comprising a wafer including a highly doped substrate of one condUctivity type having its <100> crystallographic planes at one face thereof and three layers of semiconductor material on the entire surface of said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped layer, and another layer all of opposite conductivity type, a V-groove extending through said layers into said substrate to define an island, a well extending into said island with a diffusion region of opposite conductivity type formed along the surface thereof to provide electrical connection to said highly doped layer, a diffusion region of one conductivity type extending into said another region, an emitter region of opposite conductivity type formed in said diffusion region, ohmic connections formed with said emitter region, said diffusion region, and said well diffusion region, and another V-groove extending across said island through said diffusion region to isolate said diffusion region from said well diffusion region.
Claim 2
Dependent Claim
167 words
An integrated circuit including a bipolar semiconductor device comprising a wafer including a highly doped substrate of one condUctivity type having its <100> crystallographic planes at one face thereof and three layers of semiconductor material on the entire surface of said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped layer, and another layer all of opposite conductivity type, a V-groove extending through said layers into said substrate to define an island, a well extending into said island with a diffusion region of opposite conductivity type formed along the surface thereof to provide electrical connection to said highly doped layer, a diffusion region of one conductivity type extending into said another region, an emitter region of opposite conductivity type formed in said diffusion region, ohmic connections formed with said emitter region, said diffusion region, and said well diffusion region, and another V-groove extending across said island through said diffusion region to isolate said diffusion region from said well diffusion region.
Claim 3
Dependent Claim
154 words
An integrated circuit including a bipolar semiconductor device comprising a wafer including a highly doped substrate of one conductivity type having its <100> crystallographic planes at one face thereof and three layers of semiconductor material on the entire surface of said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped layer, and another layer all of opposite conductivity type, a V-groove extending through said layers into said substrate to define an island, a well in said island extending to a point adjacent said highly doped buried layer, a diffusion region of opposite conductivity type formed at the surface of said well to provide a connection to said highly doped layer, and a diffusion region of one conductivity type formed in said another region and a closed groove extending through said diffusion region into said another region to define a diffused island on the surface of said device.
Claim 4
Dependent Claim
154 words
An integrated circuit including a bipolar semiconductor device comprising a wafer including a highly doped substrate of one conductivity type having its <100> crystallographic planes at one face thereof and three layers of semiconductor material on the entire surface of said one face, said layers comprising in order a lightly doped or intrinsic layer, a highly doped layer, and another layer all of opposite conductivity type, a V-groove extending through said layers into said substrate to define an island, a well in said island extending to a point adjacent said highly doped buried layer, a diffusion region of opposite conductivity type formed at the surface of said well to provide a connection to said highly doped layer, and a diffusion region of one conductivity type formed in said another region and a closed groove extending through said diffusion region into said another region to define a diffused island on the surface of said device.
Claim 5
Dependent Claim
137 words
A single crystal silicon wafer integrated circuit including a plurality of bipolar NPN transistor islands comprising: a P-type silicon substrate; a heavily doped N-type buried layer epitaxially formed over the silicon substrate layer; an N-type collector layer epitaxially formed over the buried layer; a P-type base region over at least a portion of the collector layer; a V-groove therearound extending into the substrate for isolating the island from the adjacent islands; an N-type emitter region diffused into the base region; a V-groove well extending into the island and having a N-doped surface for providing electrical access to the collector layer; an insulative layer over the island; and conductive leads extending through the insulative layer in electrical connection with the base region, with the emitter region, and with the collector region through the doped surface of the well.
Claim 6
Dependent Claim
137 words
A single crystal silicon wafer integrated circuit including a plurality of bipolar NPN transistor islands comprising: a P-type silicon substrate; a heavily doped N-type buried layer epitaxially formed over the silicon substrate layer; an N-type collector layer epitaxially formed over the buried layer; a P-type base region over at least a portion of the collector layer; a V-groove therearound extending into the substrate for isolating the island from the adjacent islands; an N-type emitter region diffused into the base region; a V-groove well extending into the island and having a N-doped surface for providing electrical access to the collector layer; an insulative layer over the island; and conductive leads extending through the insulative layer in electrical connection with the base region, with the emitter region, and with the collector region through the doped surface of the well.
Claim 7
Dependent Claim
32 words
The integrated circuit of claim 3, wherein a lightly layer or intrinsic layer is provided between the substrate and the buried layer, and epitaxially interfacing with the substrate and the buried layer.
Claim 8
Dependent Claim
15 words
The integrated circuit of claim 4, wherein the base region extends over the entire island.
Claim 9
Dependent Claim
47 words
The integrated circuit of claim 5, wherein a divider V-groove extends into the island deeper than the base region and extends across the island separating that portion of the island having the emitter region from that portion of the island having the well with the doped surface.
Claim 10
Dependent Claim
24 words
The integrated circuit of claim 5, wherein another V-groove well extends through the base region and forms a Schottky diode with the collector layer.
Claim 11
Dependent Claim
55 words
The integrated circuit of claim 5, wherein at least a portion of the bipolar transistors are PNP type and are formed by providing a closed V-groove in the base region to form the emitter element and the collector element of the PNP transistor, and the collector layer forms the base element of the PNP transistor.
Claim 12
Dependent Claim
30 words
The integrated circuit oF claim 4, wherein the base region extends over only a portion of the island and is formed by diffusion of P-type dopants into the collector layer.
Claim 13
Dependent Claim
31 words
The integrated circuit of claim 9, wherein at least a portion of the bipolar transistors are PNP type and are formed by spaced diffusions of P-type dopants into the collector layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-14 | 1978-10-14 | 1979-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-14 | 1982-10-14 | 1983-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-14 | 1986-10-14 | 1987-04-15 | $7700.00 | Window Closed / Lapsed |