Correlation circuit including vernier

Claim 2

In combination with a pair of gates for sampling substantially identical binary quantized waveforms, means for unblocking one of the gates at a predetermined sampling rate and for unblocking the other gate at said sampling rate in any selected one of several phase relationships relative to the unblocking of said one gate wherein said several phase relationships include in-phase and out of phase by one of several equal step fractional divisions of the sampling period, means triggered by the first means in coincidence with the unblocking of the one gate for further delaying the output of the other gate by an interval equal to the compliment of the fraction of the sampling period by which the output of the other gate is delayed, and means triggered by the first means in coincidence with the unblocking of the first gate for delaying the output of the one gate by one sampling period.

Claim 3

The combination defined in claim 1 further comprising, additional delay means triggered by the first means in coincidence with the unblocking of the first gate for further delaying the output of said one gate by an interval equal to any selected one of a plurality of integral multiples of the sampling period including zero, and correlation means coupled to the outputs of said complimentary period delay means and said additional delay means triggered by the first means in coincidence with the unblocking of the first gate.

Claim 4

An improved signal correlation system comprising two essentially identical signal waveform detectors for intercepting signals from the same source, separate means for converting the signal waveforms from the respective detectors into squared binary waveforms wherein the lows are in time coincidence with those levels of the respective signal waveforms which are to one side of a selected reference level, a first and second gate coupled to the outputs of the separate means for normally blocking the binary waveform outputs and for unblocking in coincidence with applied gating pulses, means for providing a first train of pulses having a particular pulse repetition frequency wherein pulse length is approximately one-sixteenth of the pulse period, and providing a plurality of additional trains of pulses onE of which has the same period as said first pulse train and the others having periods that are one-half, one-quarter and one-eighth of the period of the first train of pulses and wherein the leading edges of pulses in the first pulse train coincide with the leading edges of pulses in each of the other pulse trains, and wherein the pulse lengths in each of the additional trains of pulses are one-half the pulse period of the respective additional train, means for coupling said first pulse train to said first gate for unblocking the first gate, selective stepwise fractional period delay means coupled to said pulse providing means and having eight operating conditions for delivering a pulse train to the second gate identical to said first pulse train displaced relative thereto n/8 period, where n is any one of 0,1,2, 3, 5, 6, 7, an encoder for setting said selective stepwise fractional period delay means to one of its operating conditions, a selectable delay shift register coupled to said first pulse train output of said pulse providing means to delay the sampling from said first gate a number of periods of said first pulse train, a shift register delay selector coupled to said encoder and to said selectable delay shift register for selecting the delay of said shift register and for delivering the delayed output, a complimentary fractional period delay means coupled to the output of said second gate and to said first pulse train output of said pulse providing means to delay the sampling from said second gate by an amount which is the compliment of the fraction of the period of delay introduced into the sampling of the second gate relative to the sampling of the first gate, means coupled to said one pulse train output of said pulse providing means for further delaying the sampling delivered by said first gate by one pulse period of said first pulse train, and means coupled to the output of said complimentary fractional period delay means and to the output of said shift register delay selection means for indicating signal waveform correlation.

Claim 5

An improved signal correlation system comprising two essentially identical signal waveform detectors for intercepting signals from the same source, separate means for converting the signal waveforms from the respective detectors into squared binary waveforms wherein the lows are in time coincidence with those levels of the respective signal waveforms which are to one side of a selected reference level, a first and second gate coupled to the outputs of the separate means for normally blocking the binary waveform outputs and for unblocking in coincidence with applied gating pulses, means for providing a first train of pulses having a particular pulse repetition frequency wherein pulse length is approximately one-sixteenth of the pulse period, and providing a plurality of additional trains of pulses onE of which has the same period as said first pulse train and the others having periods that are one-half, one-quarter and one-eighth of the period of the first train of pulses and wherein the leading edges of pulses in the first pulse train coincide with the leading edges of pulses in each of the other pulse trains, and wherein the pulse lengths in each of the additional trains of pulses are one-half the pulse period of the respective additional train, means for coupling said first pulse train to said first gate for unblocking the first gate, selective stepwise fractional period delay means coupled to said pulse providing means and having eight operating conditions for delivering a pulse train to the second gate identical to said first pulse train displaced relative thereto n/8 period, where n is any one of 0,1,2, 3, 5, 6, 7, an encoder for setting said selective stepwise fractional period delay means to one of its operating conditions, a selectable delay shift register coupled to said first pulse train output of said pulse providing means to delay the sampling from said first gate a number of periods of said first pulse train, a shift register delay selector coupled to said encoder and to said selectable delay shift register for selecting the delay of said shift register and for delivering the delayed output, a complimentary fractional period delay means coupled to the output of said second gate and to said first pulse train output of said pulse providing means to delay the sampling from said second gate by an amount which is the compliment of the fraction of the period of delay introduced into the sampling of the second gate relative to the sampling of the first gate, means coupled to said one pulse train output of said pulse providing means for further delaying the sampling delivered by said first gate by one pulse period of said first pulse train, and means coupled to the output of said complimentary fractional period delay means and to the output of said shift register delay selection means for indicating signal waveform correlation.