US3878008A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming high reliability mesa diode
Assignee: United States Department of the Navy
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Filing: 1974-02-25
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Granted: 1975-04-15
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Expires: 1994-02-25
Abstract
Abstract An improved semiconductor device and technique for fabricating diced mesas in a semiconductor wafer. Two metal layers are coated over the active surface of a semiconductor wafer and etched using standard photoresist techniques to define specific metal dot areas. The wafer is subsequently etched to facilitate dicing of the wafer and reduce wafer thickness. Using the metal dots as masks and differential etches, the contact metal is etched to recede beyond the mesa edge to form the top contact on a semiconductor device having low parasitic capacitance and high resistance to edge breaking and metal shorting of the semiconductor junction.
Inventors
- 👤 K Reed Gleason
- 👤 Marvin L Bark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 09:13
CPC Classifications
H; H10; H10P; H10P95/00; H10D; H10D99/00; H10P50/00; H10P50/69; H10P50/691; H10P50/692; H10P50/693; H10P50/694; Y; Y10; Y10S; Y10S257/00; Y10S257/926; Y10S438/00; Y10S438/928; Y10S438/977
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
226 words
A METHOD OF PRODUCING A DICED MESA SEMICONDUCTOR DEVICE COMPRISING: A. FORMING A SEMICONDUCTOR WAFER HAVING AN ACTIVE SURFACE FORMING ONE OF TWO OPPOSED WAFER SURFACES, A FIRST METAL LAYER BONDED TO THE ACTIVE SURFACE OF SAID WAFER AND A SECOND METAL LAYER BONDED TO THE SURFACE OF SAID FIRST LAYER; B. ETCHING SAID SECOND LAYER TO FORM AT LEAST ONE FIRST METAL DOT ON THE SURFACE OF SAID FIRST LAYER; C. DEPOSITING A METAL CONTACT BUTTON ON SAID AT LEAST ONE METAL DOT; D. ETCHING A PLURALITY OF GRID LINES IN SAID FIRST LAYER AND IN SAID WAFER TO DELINEATE A CHIP CONTAINING SAID AT LEAST ONE FIRST METAL DOT; E. ETCHING SAID FIRST LAYER TO FORM A SECOND METAL DOT CONCENTRIC WITH SAID AT LEAST ONE FIRST METAL DOT; F. ETCHING SAID WAFER USING SAID SECOND METAL DOT AS A MASK TO FORM A MESA AND THEIN SAID WAFER ALONG SAID GRID LINES; G. ETCHING SAID SECOND METAL DOT TO A DIAMETER ABOUT EQUAL TO THE DIAMETER OF SAID AT LEAST ONE FIRST DOT USING SAID FIRST DOT AS A MASK; H. AGAIN ETCHING THE WAFER USING SAID DOTS AS A MASK WHEREBY UNDERCUTTING OF THE DOTS OCCURS; I. ETCHING SAID SECOND DOT SO AS TO PREVENT METAL OVERHANG AT THE MESA EDGE; J. ETCHING SAID FIRST DOT USING SAID BUTTON AS A MASK.
Claim 2
Independent Claim
226 words
A METHOD OF PRODUCING A DICED MESA SEMICONDUCTOR DEVICE COMPRISING: A. FORMING A SEMICONDUCTOR WAFER HAVING AN ACTIVE SURFACE FORMING ONE OF TWO OPPOSED WAFER SURFACES, A FIRST METAL LAYER BONDED TO THE ACTIVE SURFACE OF SAID WAFER AND A SECOND METAL LAYER BONDED TO THE SURFACE OF SAID FIRST LAYER; B. ETCHING SAID SECOND LAYER TO FORM AT LEAST ONE FIRST METAL DOT ON THE SURFACE OF SAID FIRST LAYER; C. DEPOSITING A METAL CONTACT BUTTON ON SAID AT LEAST ONE METAL DOT; D. ETCHING A PLURALITY OF GRID LINES IN SAID FIRST LAYER AND IN SAID WAFER TO DELINEATE A CHIP CONTAINING SAID AT LEAST ONE FIRST METAL DOT; E. ETCHING SAID FIRST LAYER TO FORM A SECOND METAL DOT CONCENTRIC WITH SAID AT LEAST ONE FIRST METAL DOT; F. ETCHING SAID WAFER USING SAID SECOND METAL DOT AS A MASK TO FORM A MESA AND THEIN SAID WAFER ALONG SAID GRID LINES; G. ETCHING SAID SECOND METAL DOT TO A DIAMETER ABOUT EQUAL TO THE DIAMETER OF SAID AT LEAST ONE FIRST DOT USING SAID FIRST DOT AS A MASK; H. AGAIN ETCHING THE WAFER USING SAID DOTS AS A MASK WHEREBY UNDERCUTTING OF THE DOTS OCCURS; I. ETCHING SAID SECOND DOT SO AS TO PREVENT METAL OVERHANG AT THE MESA EDGE; J. ETCHING SAID FIRST DOT USING SAID BUTTON AS A MASK.
Claim 3
Dependent Claim
43 words
The method of claim 1 wherein said metal dot of step (b) is formed of greater diameter than the button of step (c) and wherein the metal dot of step (e) is formed of greater diameter than the metal dot of step (b).
Claim 4
Dependent Claim
37 words
The method of claim 1 further including metallizing the other surface of said wafer after step (e) and applying a support thereto, and etching said wafer in step (f) to separate said wafer along said grid lines.
Claim 5
Dependent Claim
23 words
The method of claim 3 wherein prior to metallizing the wafer, the other surface is lapped to reduce the thickness of the wafer.
Claim 6
Dependent Claim
45 words
The method of claim 1 wherein said wafer is silicon having an active surface region forming a Trapped-Plasma-Avalanche-Transit-Time diode structure, the first metal layer is chromium and the second metal layer is gold, and the layers are formed over the entire surface of the wafer.
Claim 7
Dependent Claim
36 words
The method of claim 1 wherein the etching of steps (b), (d) and (e) are performed using a photoresist mask and wherein the depositing of step (c) comprises electroplating a gold button using a photoresist mask.
Claim 8
Dependent Claim
69 words
The method of claim 1 wherein said step of forming at least one first metal dot forms a plurality of spaced first metal dots, said step of forming a metal button forms a gold button on each of said plurality of first metal dots, and said step of forming a concentric second metal dot forms a second metal dot concentric with each of said plurality of first metal dots.
Claim 9
Dependent Claim
29 words
The method of claim 7 wherein said plurality of grid lines define lines separating said wafer into a plurality of chips with each chip having plural metal dot areas.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-14 | 1978-10-14 | 1979-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-14 | 1982-10-14 | 1983-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-14 | 1986-10-14 | 1987-04-15 | $7700.00 | Window Closed / Lapsed |