Adaptable moving target processor

Claim 2

A moving target processor for analyzing received signals from a pulsed radar system comprising: program control means for generating a control signal which is representative of predicted spectral characteristics of the received signal; weighting means for processing the received signal therethrough with a variable gain programmed in response to the control signal; and means for filtering the weighted received signal, said filtering means having a variable frequency response programmed in response to the control signal.

Claim 3

The processor of claim 1 further comprising integrator means for integrating the filtered signal generated by said filter means, said integrator means having an integration time period which is variable in response to the control signal.

Claim 4

The processor of claim 2 further comprising detector means for comparing the integrated video signals generated by said integrator means to a threshold signal level, said detector means including means for varying the threshold signal level in response to the control signal.

Claim 5

An adaptive moving target processor for discriminating between stationary and moving targets, located at a plurality of range intervals, in response to received signals coupled thereto from a receiver, comprising: a program controller for generating control signals representative of the spectral width of the received signals corresponding to stationary targets; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit; and an adaptive clutter rejection filter having an input circuit coupled to said weighted signal output circuit, having a filter control input circuit coupled to said program controller, and having an output circuit.

Claim 6

An adaptive moving target processor for discriminating between stationary and moving targets, located at a plurality of range intervals, in response to received signals coupled thereto from a receiver, comprising: a program controller for generating control signals representative of the spectral width of the received signals corresponding to stationary targets; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit; and an adaptive clutter rejection filter having an input circuit coupled to said weighted signal output circuit, having a filter control input circuit coupled to said program controller, and having an output circuit.

Claim 7

The processor of claim 4 wherein said adaptive clutter rejection filter comprises delay means for super-positioning N successive weighted signals from the same range interval for each of a plurality of range intervals, and where the value of the number N is controlled in response to the control signals coupled from said program controller.

Claim 8

The processor of claim 5 wherein said received signals are coupled from a system having an antenna for radiating energy in a pattern and said program controller comprises means for controlling the control signal as a function of the doppler frequency shift across the antenna pattern.

Claim 9

The processor of claim 6 further comprising an integrator having a signal input circuit coupled to the output circuit of said adaptive clutter rejection filter, having an integration control input circuit coupled to said program controller and having an output circuit.

Claim 10

The processor of claim 7 further comprising a mean-level threshold detector having a signal input circuit, a signal output circuit and a threshold control circuit coupled to said program controller.

Claim 11

An adaptive moving target processor for discriminating between stationary and moving targets in response to received signals from a plurality of range intervals coupled from a receiver comprising: a program controller for generating control signals representative of the spectral width of the received signals corresponding to stationary targets; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit; an analog-to-digital converter having an input circuit coupled to said weighted signal output circuit of said weighting function generator and having an output circuit; and an adaptive clutter rejection filter having an input circuit coupled to said analog-to-digital converter output circuit, having a filter control input circuit coupled to said program controller, and having a signal output circuit.

Claim 12

An adaptive moving target processor for discriminating between stationary and moving targets in response to received signals from a plurality of range intervals coupled from a receiver comprising: a program controller for generating control signals representative of the spectral width of the received signals corresponding to stationary targets; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit; an analog-to-digital converter having an input circuit coupled to said weighted signal output circuit of said weighting function generator and having an output circuit; and an adaptive clutter rejection filter having an input circuit coupled to said analog-to-digital converter output circuit, having a filter control input circuit coupled to said program controller, and having a signal output circuit.

Claim 13

The processor of claim 9 wherein said received signals are coupled from a system having an antenna for radiating energy in a pattern and said program controller comprises means for controlling the control signal as a function of the doppler frequency shift across the antenna pattern.

Claim 14

The processor of claim 9 wherein said adaptive clutter rejection filter comprises digital filter means for superpositioning, with alternate polarity, N successive weighted signals from the same range interval for each of a plurality of range intervals, and where N is controlled in response to the control signals coupled from said program controller.

Claim 15

The processor of claim 11 wherein said digital filter means includes: a digital accumulator having a first input circuit coupled to the input circuit of said adaptive clutter rejection filter, having a second input circuit and having an output circuit; digital delay means having an input circuit coupled to said output circuit of said accumulator and having an output circuit; a filter gating circuit having an input circuit coupled to the output circuit of said digital delay means, having a first output circuit, having a second output circuit coupled to said second input circuit of said accumulator and having a filter gate control input circuit; and a filter control circuit having an output circuit coupled to said filter gate control input circuit and having an input circuit coupled to said program controller.

Claim 16

The processor of claim 11 wherein said digital filter means includes: a digital subtractor having a first input circuit coupled to the input circuit of said adaptive digital clutter rejection filter, having a second input circuit and having a difference output circuit; a multi-bit shift register having an input circuit coupled to said difference output circuit and having an output circuit; a filter gating circuit having an input circuit coupled to the output circuit of said shift register, having a first output circuit, having a second output circuit coupled to said second input circuit of said subtractor, and having a filter gate control input circuit; and a filter control circuit having an output circuit coupled to said filter gate control input circuit and having an input circuit coupled to said program controller.

Claim 17

The processor of claim 13 wherein said shift register comprises a plurality of stages and the number of stages is equal to the number of range intervals processed by said processor.

Claim 18

The processor of claim 13 wherein said digital delay means includes a multi-bit shift register having a plurality of stages, the number of stages in said shift register being essentially equal to, and less than twice the number of range intervals processed by said processor.

Claim 19

The processor of claim 13 wherein said digital delay means includes a digital memory device with a storage capacity of essentially twice, and less than four times, the number of range intervals to be processed.

Claim 20

The processor of claim 9 further comprising an integrator having a signal input circuit coupled to the signal output circuit of said adaptive clutter rejection filter, having an integration control input circuit coupled to said program controller and having an output circuit.

Claim 21

The processor of claim 17 wherein said integrator comprises: a first digital adder having a first input circuit coupled to the signal input circuit of said video integrator, having a second input circuit, and having a sum output circuit; a shift register having an input circuit coupled to the sum circuit of said first adder and having an output circuit; and feedback means for coupling the output circuit of said shift register to the second input circuit of said first adder, said feedback means having a control input circuit coupled to said program controller for varying the feedback gain therethrough in response to said control signal generated by said program controller.

Claim 22

The processor of claim 17 further comprising a mean level threshold detector having a signal input circuit, a signal output circuit and a threshold control circuit coupled to said program controller.

Claim 23

The processor of claim 17 further including a mean level threshold detector comprising: means, coupled to the output circuit of said video integrator, for generating a threshold signal representative of the mean value of the output signal of said video integrator; delay means for delaying the output signal of said video integrator, said delay means having an input circuit coupled to said output circuit of said video integrator and having an output circuit; a comparator having a signal input circuit coupled to the output circuit of said delay means, having a threshold input circuit, and having an output circuit; and variable multiplier means for varying the gain therethrough in response to said program controller, said multiplier means being coupled between the output circuit of said means for generating a threshold signal and the threshold input circuit of said comparator.

Claim 24

Processor of claim 19 wherein said digital mean level threshold detector comprises: a first shift register having an input circuit coupled to the output circuit of said video integrator, having a first output circuit and a second output circuit; a subtractor having a first input circuit coupled to the first output circuit of said first shift register, having a second input circuit coupled to the output circuit of said integrator, and having a difference output circuit; an adder having a first input circuit coupled to the difference output circuit of said subtractor, having a second input circuit and having a sum output circuit; a second shift register having an input circuit coupled to the sum output circuit of said adder and having an output circuit coupled to said second input circuit of said adder; a comparator having a signal input circuit coupled to the second output circuit of said first shift register, having a threshold input circuit, and having a moving target output circuit; and variable multiplier means for varying the gain therethrough in response to said program controller, said multiplier means being coupled between the output circuit of the one-stage shift register and the threshold input circuit of the comparator.

Claim 25

In combination with a pulsed radar system, mounted on a vehicle capable of moving at a velocity V, and having an antenna for radiating energy at an angle .theta. relative to the direction of motion of said vehicle, a moving target processor for discriminating moving targets from stationary targets in each of a plurality of range intervals in response to received signals from a radar receiver comprising: a program controller for generating control signals indicative of the spectral width of the received signals corresponding to stationary targets, said program signals being a function of the velocity V and angle .theta.; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit, said weighting function generator including means for processing the received video therethrough with a variable programmed gain each radar interpulse period in response to said control signal; an analog-to-digital converter having an input circuit coupled to said weighted signal output circuit of said weighting function generator and having an output circuit; an adaptive digital clutter rejection filter having an input circuit coupled to said analog-to-digital converter output circuit, having a filter control input circuit coupled to said program controller, and having a signal output circuit, said adaptive digital clutter rejection filter comprising digital filter means for superpositioning, with alternating polarity, N successive weighted signals from the same range interval of each of a plurality of range intervals, and where the value of the number N is controlled in response to the control signals coupled from said program controller; an integrator having a signal input circuit coupled to the signal output circuit of said adaptive digital clutter rejection filter, having an integration control input circuit coupled to said program controller and having an output circuit; and a mean level threshold detector having a signal input circuit, a signal output circuit and a threshold control circuit coupled to said program controller.

Claim 26

In combination with a pulsed radar system, mounted on a vehicle capable of moving at a velocity V, and having an antenna for radiating energy at an angle .theta. relative to the direction of motion of said vehicle, a moving target processor for discriminating moving targets from stationary targets in each of a plurality of range intervals in response to received signals from a radar receiver comprising: a program controller for generating control signals indicative of the spectral width of the received signals corresponding to stationary targets, said program signals being a function of the velocity V and angle .theta.; a weighting function generator having an input circuit coupled to said radar receiver, having a weighting generator control input circuit coupled to said program controller, and having a weighted signal output circuit, said weighting function generator including means for processing the received video therethrough with a variable programmed gain each radar interpulse period in response to said control signal; an analog-to-digital converter having an input circuit coupled to said weighted signal output circuit of said weighting function generator and having an output circuit; an adaptive digital clutter rejection filter having an input circuit coupled to said analog-to-digital converter output circuit, having a filter control input circuit coupled to said program controller, and having a signal output circuit, said adaptive digital clutter rejection filter comprising digital filter means for superpositioning, with alternating polarity, N successive weighted signals from the same range interval of each of a plurality of range intervals, and where the value of the number N is controlled in response to the control signals coupled from said program controller; an integrator having a signal input circuit coupled to the signal output circuit of said adaptive digital clutter rejection filter, having an integration control input circuit coupled to said program controller and having an output circuit; and a mean level threshold detector having a signal input circuit, a signal output circuit and a threshold control circuit coupled to said program controller.

Claim 27

The processor of claim 22 wherein said adaptive digital clutter rejection filter means includes: a first digital subtractor having a first input circuit coupled to the input circuit of said adaptive digital clutter rejection filter, having a second input circuit and having a difference output circuit; a first multi-bit shift register having an input circuit coupled to said difference output circuit and having an output circuit, said shift register comprising a plurality of stages and the number of stages being essentially equal to, and less than twice the number of range intervals processed by said processor; a filter gating circuit having an input circuit coupled to the output circuit of said shift register, having a first output circuit, having a second output circuit coupled to said second input circuit of said first subtractor, and having a filter gate control input circuit; and a filter control circuit having an output circuit coupled to said filter gate control input circuit and having an input circuit coupled to said program controller.

Claim 28

The processor of claim 22 wherein said integrator comprises: a first digital adder having a first input circuit coupled to the signal input circuit of said video integrator, having a second input circuit, and having a sum output circuit; a second shift register having an input circuit coupled to the sum circuit of said first adder and having an output circuit; and feedback means for coupling the output circuit of said second shift register to the second input circuit of said first adder, said feedback means having a control input circuit coupled to said program controller for varying the feedback gain therethrough in response to said control signal generated by said program controller.

Claim 29

Processor of claim 22 wherein said digital mean level threshold detector comprises: a third shift register having an input circuit coupled to the output circuit of said video integrator, having a first output circuit and a second output circuit; a second subtractor having a first input circuit coupled to the first output circuit of said third shift register, having a second input circuit coupled to the output circuit of said integrator, and having a difference output circuit; a second digital adder having a first input circuit coupled to the difference output circuit of said second subtractor, having a second input circuit and having a sum output circuit; a fourth one-stage shift register having an input circuit coupled to the sum output circuit of said adder and having an output circuit coupled to said second input circuit of said adder; a comparator having a signal input circuit coupled to the second output circuit of said third shift register, having a threshold input circuit, and having a moving target output circuit; and variable multiplier means for varying the gain therethrough in response to said program controller, said multiplier means being coupled between the output circuit of the fourth shift register and the threshold input circuit of the comparator.