Electronic timer

Claim 2

A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and to thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said counter means including a plurality of interconnected decade counters, said memory means including a plurality of latches for remembering instantaneous settings of said decade counters respectively, said control means including an element manually actuable to operate said latches to remember an instantaneous count in said decade counters without interrupting operation of the decade counters, so that the decade counters count both before and after actuation of the latches, said display means including multiplexer means responsive to said latches to produce multiplexed binary coded decimal signals representing the settings of said latches respectively, and means for producing a plurality of display digits dependent upon said signals and representing decimally the times remembered by said latches.

Claim 3

A timer as recited in claim 1, in which said signals from said multiplexer means represent times in seconds, there being circuitry connected to said multiplexer means and responsive to said signals therefrom and operable to reset said counters upon attainment of the sixty second count.

Claim 4

A timer as recited in claim 1, in which said signals from said multiplexer means represent a seconds count, there being means responsive to said signals upon attainment of a sixty second count to produce a minutes display.

Claim 5

A timer as recited in claim 1, including circuitry for resetting said counter means automatically upon each actuation of said control means, said circuitry containing switching means operable to disable the circuitry to selectively condition the counter means either for said automatic resetting upon actuation of the control means or for a continued count without resetting upon actuation of the control means.

Claim 6

A timer as recited in claim 1, in which said element is a first manually actuable switch for actuating said latches to remember an instantaneous count without interrupting operation of the decade counters, said control means including also a second separately manually actuable switch operable to actuate said latches to remember an instantaneous setting in the counter means, there being circuitry operable upon actuation of said second switch to reset said decade counters.

Claim 7

A timer as recited in claim 1, in which said element is a first manually actuable switch, said control means including also a first shift register actuable by said switch, a second shift register, a second separately manually operable switch for actuating said second shift register, circuitry operable by said second shift register upon actuation of said second switch to actuate said latches to instantaneously remember the setting of said decade counters, and then reset the counters, and additional circuitry actuable by said first shift register upon operation of said first switch to actuate said latches to remember the instantaneous setting of said decade counters, without resetting of the counters.

Claim 8

A timer as recited in claim 6, in which said first mentioned circuitry contains a disabling switch for selectively conditioning said circuitry to either reset the counter means as stated or avoid such resetting upon operation of the corresponding shift register.

Claim 9

A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and to thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said pulse generating means including an oscillator and a frequency divider actuable thereby, said counter means including a plurality of interconnected decade counters representing decimally a time in seconds, said memory means including a plurality of latches for remembering the instantaneous settings of said different counters respectively, said control means including a manually actuable switch for determining the instant at which a time reading is to be taken, a one shot multivibrator actuable by said switch and acting to maintain each of said displays for a predetermined interval and then automatically discontinue the display, a shift register operable upon actuation of said switch to first actuate said latches to remember the instantaneous setting of said counter, and then automatically reset said counters to zero, said display means including a multiplexer responsive to said latches and having output lines carrying multiplexed signals representing the settings of said latches, a decoder responsive to said signals, and means actuable by said decoder to produce a series of display digits representing decimally the setting of said latches in seconds.

Claim 10

A timer comprising means for generating a series of uniformly timed pulses, counter means for counting said pulses, memory means actuable by said counter means to conditions representing different counts instantaneously attained by said counter means, control means for actuating said memory means at different selected times to remember said instantaneous counts, and display means for producing displays representing said instantaneous counts, said counter means being operable to count said pulses continuously up to a first of said times for inclusion in a first of said displays and to thereafter continue to count said pulses from said first time to the next successive one of said selected times for inclusion in the next successive one of said displays, said pulse generating means including an oscillator and a frequency divider actuable thereby, said counter means including a plurality of interconnected decade counters representing decimally a time in seconds, said memory means including a plurality of latches for remembering the instantaneous settings of said different counters respectively, said control means including a manually actuable switch for determining the instant at which a time reading is to be taken, a one shot multivibrator actuable by said switch and acting to maintain each of said displays for a predetermined interval and then automatically discontinue the display, a shift register operable upon actuation of said switch to first actuate said latches to remember the instantaneous setting of said counter, and then automatically reset said counters to zero, said display means including a multiplexer responsive to said latches and having output lines carrying multiplexed signals representing the settings of said latches, a decoder responsive to said signals, and means actuable by said decoder to produce a series of display digits representing decimally the setting of said latches in seconds.

Claim 11

A timer as recited in claim 8, including additional counter means actuable by said shift register upon each actuation of said switch to count the number of actuations of the switch.

Claim 12

A timer as recited in claim 8, including means actuable by said signals from said multiplexer and responsive to the attainment of a sixty second count to automatically reset said counters, and means responsive to said last mentioned means to produce a digital display representing minutes timed.

Claim 13

A timer as recited in claim 10, in which said control means include an additional switch actuable manually and separately from said first switch, and an additional shift register actuable by said additional switch to actuate said latches to remember the settings of said counters but to do so without resetting of the counters.