US3876833A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Receiver for synchronous data signals, including a detector for detecting transmission speed changes
Assignee: Telecommunications Radioelectriques et Telephoniques SA TRT
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Filing: 1973-11-08
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Granted: 1975-04-08
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Expires: 1993-11-08
Abstract
Abstract A receiver in a synchronous data transmission system, in which the data may be transmitted at least at two speeds differing by an integral factor N, is provided with a speed change detector. This detector comprises first and second circuits for detecting speeds lower and higher than the local clock rate, the first circuit including a pulse distributor actived by the local clock pulses for distributing pulses at data signal transitions over its N outputs, each of which is connected to a logic circuit of the NAND-type through a circuit detecting the presence of pulses, the second circuit including a data signal sampler activated at the local clock rate, a sample analyzer producing output pulses only for predetermined sample values and a circuit detecting the presence of pulses at the analyzer output. The speed change detector may be used for automatically adjusting the receiver to the speed of the received data.
Inventors
- 👤 Pierre Louis Vincent Breant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:49
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04J; H04J3/00; H04J3/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
201 words
A receiver in a system for synchronous data transmission in which the data signals may be transmitted at least at two transmission speeds differing by a factor N, where N is an integer, said receiver being provided with a transition detector for generating pulses at transitions in the received data signal, a clock pulse generator included in a phase control loop to which the pulses from the transition detector are applied for controlling the phase of the clock pulses with the transitions of the received data signal, and a detector for detecting changes in the transmission speed of the received data signal, said speed change detector being provided with a circuit for detecting a decrease in the transmission speed by a factor N, said circuit including a pulse distributor controlled by the clock pulse generator for distributing the pulses from the transition detector in the rhythm of the clock pulses over N outputs, each of said outputs being connected through a circuit means for detecting the presence of pulses to logic selection gate, said gate generating an output signal when said circuit means detects the absence of pulses from at least at one of the N outputs of the pulse distributor.
Claim 2
Dependent Claim
201 words
A receiver in a system for synchronous data transmission in which the data signals may be transmitted at least at two transmission speeds differing by a factor N, where N is an integer, said receiver being provided with a transition detector for generating pulses at transitions in the received data signal, a clock pulse generator included in a phase control loop to which the pulses from the transition detector are applied for controlling the phase of the clock pulses with the transitions of the received data signal, and a detector for detecting changes in the transmission speed of the received data signal, said speed change detector being provided with a circuit for detecting a decrease in the transmission speed by a factor N, said circuit including a pulse distributor controlled by the clock pulse generator for distributing the pulses from the transition detector in the rhythm of the clock pulses over N outputs, each of said outputs being connected through a circuit means for detecting the presence of pulses to logic selection gate, said gate generating an output signal when said circuit means detects the absence of pulses from at least at one of the N outputs of the pulse distributor.
Claim 3
Dependent Claim
153 words
A receiver as claimed in claim 1, characterized in that the speed change detector is also provided with a circuit for detecting an increase in the transmission speed by a factor N, said circuit including a circuit for sampling the received data signal, said circuit being controlled by a pulse generator connected to the clock pulse generator for generating a sampling pulse at least at one of the instants T/N, 2T/N, . . . . . , (N-1)T/N after the instant of occurrence of each clock pulse, where T is the period of the clock pulses, a sample analyzer connected to the sampling circuit, said analyzer only generating pulses for samples substantially corresponding to crossings of the received data signal through a given reference level, and a circuit for detecting the presence of pulses at the output of the sample analyzer and for generating an output signal in the presence of said pulses.
Claim 4
Dependent Claim
134 words
A receiver as claimed in claim 1 provided with a data detector in the form of an integrate-and-dump circuit controlled by the clock pulse generator, characterized in that the speed change detector is also provided with a circuit for detecting an increase in the transmission speed by a factor N, said circuit including a sampling circuit controlled by the clock pulse generator for sampling the output signal from the data detector, a sample analyzer connected to the sampling circuit, said analyzer only generating pulses for samples having an absolute value which is lower than (N-1)/N times the maximum absolute value of the data detector output signal, and a circuit for detecting the presence of pulses at the output of the sample analyzer and for generating an output signal in the presence of said pulses.
Claim 5
Dependent Claim
91 words
A receiver as claimed in claim 1, characterized in that the circuit means for detecting the presence of pulses comprises an operational amplifier connected as an integrator, said operational amplifier including an integration capacitor shunted by a resistor for obtaining a decay time constant for the integration signal which is much longer than the time interval between the pulses occurring at the input of said circuit, and a threshold circuit connected to said operational amplifier said circuit generating an output signal when its threshold level is exceeded by the integration signal.
Claim 6
Dependent Claim
102 words
A receiver as claimed in claim 1, characterized in that the circuit means for detecting the presence of pulses comprises an up-down counter having a forward input and a reverse input, one of the two inputs being connected to a pulse generator for generating pulses with a period which is much longer than the time interval between the pulses which occur at the input of the circuit and which are applied to the other input of the updown counter, and an extreme count position decoder, connected to the up-down counter, the output of said decoder output comprising the output of the circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-07 | 1978-10-07 | 1979-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-07 | 1982-10-07 | 1983-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-07 | 1986-10-07 | 1987-04-08 | $7700.00 | Window Closed / Lapsed |