US3875386A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Zero suppression circuit
Assignee: Hitachi Ltd
•
Filing: 1973-10-04
•
Granted: 1975-04-01
•
Expires: 1993-10-04
Abstract
Abstract A zero suppression circuit for a display of an electronic calculator or the like employs a register which includes n flipflops for storing a decimal point signal and signals representing whether the digits of respective places are any of the digits 1 to 9, and a detector circuit which includes n OR gates, the i-th gate of the detector circuit being supplied with the output signals of the first to i-th flip-flops of the register. An output ''''0'''' of the i-th OR gate signifies that neither a digit from 1 to 9 nor a decimal point exists in and below the i-th place, so the digit 0 in the i-th place is unnecessary. Through such a judgement, the unnecessary zeros below the decimal point are prevented from being indicated in the display. When further detector circuits are provided, unnecessary zeros in the upper places can also be prevented from being indicated.
Inventors
- 👤 Takao Tsuiki
- 👤 Yoshikazu Hatsukano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:47
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/1407
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
163 words
A zero suppression circuit comprising: first means, responsive to an input signal representative of an n-digit decimal number, and having an n element memory capacity, for storing therein respective signals representative of whether a digit of said decimal number is the digit zero, and including means for storing, in one of said elements, a signal representative of the position of a decimal point in said decimal number; and second means, responsive to the contents of said first means, for detecting the presence of the digit zero at those digit positions of said n digit decimal number which are unnecessary for completely representing said decimal number and comprising a first detector circuit including n gate circuits respectively coupled to the n memory elements of said first means, so that the outputs of the first to i-th memory elements of said first means are coupled to the i-th gate circuit of said first detector circuit, wherein 1 < OR = i < OR = n.
Claim 2
Dependent Claim
163 words
A zero suppression circuit comprising: first means, responsive to an input signal representative of an n-digit decimal number, and having an n element memory capacity, for storing therein respective signals representative of whether a digit of said decimal number is the digit zero, and including means for storing, in one of said elements, a signal representative of the position of a decimal point in said decimal number; and second means, responsive to the contents of said first means, for detecting the presence of the digit zero at those digit positions of said n digit decimal number which are unnecessary for completely representing said decimal number and comprising a first detector circuit including n gate circuits respectively coupled to the n memory elements of said first means, so that the outputs of the first to i-th memory elements of said first means are coupled to the i-th gate circuit of said first detector circuit, wherein 1 < OR = i < OR = n.
Claim 3
Dependent Claim
67 words
A circuit according to claim 1, wherein said second means comprises a second detector circuit including n gate circuits respectively coupled to the n memory elements of said first means, so that the outputs of the nth to ith memory elements of said first means are coupled to the i-th gate circuit of said second detector circuit, where 1 < or = i < or = n.
Claim 4
Dependent Claim
62 words
A circuit according to claim 2, wherein said second means further includes a third detector circuit, responsive to the outputs of said first and second detector circuits, for logically combining the respective outputs of the gate circuits thereof, and for providing an output signal representative of the presence of zeros at digit positions which are unnecessary for completely representing said decimal number.
Claim 5
Dependent Claim
28 words
A circuit according to claim 3, further including an output register, coupled to said third detector circuit for storing the output signals therefrom in n memory element positions.
Claim 6
Dependent Claim
117 words
A circuit according to claim 3, wherein said first means includes a numeral register, having n storage positions, for receiving a signal representative of a decimal number and converting said received number into an n digit decimal number, a decimal point register having n storage positions, for storing the position of a decimal point in said decimal number, and means for logically combining the contents of selected ones of the storage positions of said numeral and decimal point registers for providing an n bit signal representative of those digit positions of said n digit decimal number which are digits other than zero and the position in said n digit decimal number at which a decimal point occurs.
Claim 7
Dependent Claim
28 words
A circuit according to claim 5, further including an output register, coupled to said third detector circuit for storing the output signals therefrom in n memory element positions.
Claim 8
Dependent Claim
217 words
A zero suppression circuit comprising: first means, responsive to an input signal representative of an n digit decimal number, and having an n element memory capacity, for storing therein respective signals representative of whether a digit of said decimal number is the digit zero and including means for storing, in one of said elements, a signal representative of the position of a decimal point in said decimal number, said first means further including a numeral register, having n storage positions, for receiving a signal representative of a decimal number and converting said received number into an n digit decimal number, a decimal point register having n storage positions, for storing the position of a decimal point in said decimal number, and means for logically combining the contents of selected ones of the storage positions of said numeral and decimal point registers for providing an n bit signal representative of those digit positions of said n digit decimal number which are digits other than zero and the position in said n digit decimal number at which a decimal point occurs; and second means, responsive to the contents of said first means, for detecting the presence of said digit zero at those digit positions of said n digit decimal number which are unnecessary for completely representing said decimal number.
Claim 9
Dependent Claim
217 words
A zero suppression circuit comprising: first means, responsive to an input signal representative of an n digit decimal number, and having an n element memory capacity, for storing therein respective signals representative of whether a digit of said decimal number is the digit zero and including means for storing, in one of said elements, a signal representative of the position of a decimal point in said decimal number, said first means further including a numeral register, having n storage positions, for receiving a signal representative of a decimal number and converting said received number into an n digit decimal number, a decimal point register having n storage positions, for storing the position of a decimal point in said decimal number, and means for logically combining the contents of selected ones of the storage positions of said numeral and decimal point registers for providing an n bit signal representative of those digit positions of said n digit decimal number which are digits other than zero and the position in said n digit decimal number at which a decimal point occurs; and second means, responsive to the contents of said first means, for detecting the presence of said digit zero at those digit positions of said n digit decimal number which are unnecessary for completely representing said decimal number.
Claim 10
Dependent Claim
45 words
A circuit according to claim 7, wherein the logically combining means of said first means comprises means for logically combining the contents of the next to least significant storage position of said numeral register with the least significant storage position of said decimal point register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-31 | 1978-09-30 | 1979-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-31 | 1982-09-30 | 1983-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-31 | 1986-09-30 | 1987-04-01 | $7700.00 | Window Closed / Lapsed |