Revertive pulsing

Claim 2

In an arrangement for monitoring tip and ring telephone conductors in a sending central office to detect and signal completion of a revertive pulsing operation during which one or more successively occurring revertive pulses transmitted from a terminating central office are serially carried by the tip and ring conductors until equality is reached between the number of such revertive pulses and a registered number, apparatus operative in response to each such revertive pulse to produce a clock pulse suitable to trigger solid state digital circuitry for detecting such equality, the apparatus comprising: a terminating resistance switchably connected between the tip and ring conductors so as to complete, for the duration of the revertive pulsing operation, a loop for conducting current flowing incident to the revertive pulses; a diode bridge circuit having a pair of input nodes each being connected to an opposite end of the terminating resistance and a pair of output nodes between which unidirectional current can flow irrespective of the direction of the loop current; an optical-coupler device comprising an optical-coupler diode and an electrically isolated optical-coupler transistor, the optical-coupler diode being connected in series-circuit relationship between the pair of output nodes so that the revertive pulses cause pulses of unidirectional current to flow through the optical-coupler diode, and the optical-coupler transistor switching from a non-conductive condition to a conductive condition and back in response to each such pulse of current; and a pulse shaping circuit responsive to the cyclical switching of the optical-coupler transistor so as to produce a clock pulse per revertive pulse.

Claim 3

Apparatus according to claim 1 wherein the pulse shaping circuit includes noise rejecting Circuit means comprising a threshold detecting circuit and a time delay network coupled between the optical-coupler transistor and the threshold detecting circuit.

Claim 4

Apparatus according to claim 2 wherein the time delay network includes a capacitor and non-linear circuit element for controllably directing charging current to the capacitor whereby there is developed across the capacitor a voltage that passes the threshold of the threshold detecting circuit.

Claim 5

Apparatus according to claim 1 further comprising voltage limiting means connected between the pair of output nodes.

Claim 6

Apparatus according to claim 4 wherein the voltage limiting means comprises a series network of diodes.

Claim 7

An arrangement for monitoring tip and ring telephone conductors in a sending central office to detect and signal completion of a revertive pulsing operation during which one or more successively occurring revertive pulses transmitted from a terminating central office are serially carried by the tip and ring conductors until equality is reached between the number of such revertive pulses and a registered number, the sending central office having switching circuitry providing to the arrangement digitally encoded inputs in conventional telephone make/break format, a plurality of the inputs indicating in a parallel data code the registered number and a separate one of the inputs indicating when the parallel coded data is available, the arrangement comprising: a terminating resistance; controllable switching means for connecting the terminating resistance between the tip and ring conductors so as to complete, for the duration of the revertive pulsing operation, a loop for conducting current flowing incident to the revertive pulses; current responsive circuit means for producing a clock pulse per revertive pulse, the circuit means including a pulse shaping circuit electrically isolated from the tip and ring conductors and means responsive to current flowing in the loop for coupling a signal to be shaped by the pulse shaping circuit; a plurality of buffer circuits, each providing a binary valued signal for a respective one of the digitally encoded inputs; and solid state digital circuit means responsive to the binary valued signals and the clock pulses for controlling the switching means so as to open the loop when equality is reached between the number of such revertive pulses and the registered number, the digital circuit means including multi-state register means, means for presetting the register means in accordance with the parallel data when such data is indicated to be available, the register means changing state responsive to each clock pulse, and decoding means responsive to the register means for controlling the switching means.

Claim 8

An arrangement for monitoring tip and ring telephone conductors in a sending central office to detect and signal completion of a revertive pulsing operation during which one or more successively occurring revertive pulses transmitted from a terminating central office are serially carried by the tip and ring conductors until equality is reached between the number of such revertive pulses and a registered number, the sending central office having switching circuitry providing to the arrangement digitally encoded inputs in conventional telephone make/break format, a plurality of the inputs indicating in a parallel data code the registered number and a separate one of the inputs indicating when the parallel coded data is available, the arrangement comprising: a terminating resistance; controllable switching means for connecting the terminating resistance between the tip and ring conductors so as to complete, for the duration of the revertive pulsing operation, a loop for conducting current flowing incident to the revertive pulses; current responsive circuit means for producing a clock pulse per revertive pulse, the circuit means including a pulse shaping circuit electrically isolated from the tip and ring conductors and means responsive to current flowing in the loop for coupling a signal to be shaped by the pulse shaping circuit; a plurality of buffer circuits, each providing a binary valued signal for a respective one of the digitally encoded inputs; and solid state digital circuit means responsive to the binary valued signals and the clock pulses for controlling the switching means so as to open the loop when equality is reached between the number of such revertive pulses and the registered number, the digital circuit means including multi-state register means, means for presetting the register means in accordance with the parallel data when such data is indicated to be available, the register means changing state responsive to each clock pulse, and decoding means responsive to the register means for controlling the switching means.