US3873976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory access system
Assignee: Unisys Corp
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Filing: 1973-07-30
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Granted: 1975-03-25
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Expires: 1993-07-30
Abstract
Abstract Disclosed is a digital computer memory access system which operates to make available storage for fields of information regardless of the fixed word structure of the computer, and includes means for directing access to either end of the field by specifying the address of its containment word and the bit distance offset between the selected field end and a selected end of the word, means, if needed, for aligning the field end according to the computer word period and means for memory read and write, through a buffer, serially by bit starting at the accessed field end.
Inventors
- 👤 James Mccabe Morris
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/04
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
151 words
In a word organized computer, a memory accessing system capable of accessing a bit field, comprising: an addressor for the word which contains an end bit of the field; an identifier of the field length; a register; means responsive to said addressor to fill said register with the addressed word; an indicator of whether or not the end bit is aligned in the first or last bit position of said register; a justifier responsive to said addressor and an indication of non-alignment from said alignment indicator to shift the word in said register toward the end of said register to which the end bit is closest until said alignment indicator indicates alignment; a buffer; an identifier of the bit positions of said register containing bits of the field; and means responsive to said field-length and field-bit-position identifiers to transfer serially by bit from said register to said buffer only field bits.
Claim 2
Dependent Claim
151 words
In a word organized computer, a memory accessing system capable of accessing a bit field, comprising: an addressor for the word which contains an end bit of the field; an identifier of the field length; a register; means responsive to said addressor to fill said register with the addressed word; an indicator of whether or not the end bit is aligned in the first or last bit position of said register; a justifier responsive to said addressor and an indication of non-alignment from said alignment indicator to shift the word in said register toward the end of said register to which the end bit is closest until said alignment indicator indicates alignment; a buffer; an identifier of the bit positions of said register containing bits of the field; and means responsive to said field-length and field-bit-position identifiers to transfer serially by bit from said register to said buffer only field bits.
Claim 3
Dependent Claim
17 words
The system of claim 1; and means to return the word in said register to the memory.
Claim 4
Dependent Claim
59 words
The system of claim 1 wherein the field may consist of any number of bits up to the storage capacity of the memory; an indicator of end bit significance; and means responsive to said end-bit-significance indicator to modify said addressor to cause said fill means to fill said register sequentially with memory words containing next portions of the field.
Claim 5
Dependent Claim
21 words
The system of claim 1; and means operative simultaneously with said transfer means to restore the field bits in said register.
Claim 6
Dependent Claim
23 words
The system of claim 1; and means operative simultaneously with said transfer means to sUbstitute zeros for the field bits in said register.
Claim 7
Dependent Claim
26 words
The system of claim 1; and means operative simultaneously with said transfer means to substitute information from said buffer for the field bits in said register.
Claim 8
Dependent Claim
27 words
The system of claim 1; and means operative simultaneously with said transfer means to substitute information from an outside source for the field bits in said register.
Claim 9
Dependent Claim
38 words
The system of claim 3 wherein said addressor comprises a register having stages for storing a word address and stages for storing a number indicating the offset of the end bit from an end of the memory word.
Claim 10
Dependent Claim
22 words
The system of claim 8 wherein said addressor modifier comprises a network for incrementing and decrementing the address stored in said addressor.
Claim 11
Dependent Claim
17 words
The system of claim 8 wherein said alignment indicator comprises the offset number stored in said addressor.
Claim 12
Dependent Claim
22 words
The system of claim 9; and means to decrement said field-length identifier one unit for each bit transferred by said transfer means.
Claim 13
Dependent Claim
18 words
The system of claim 11 wherein said network is responsive to only non-zero content in said field-length identifier.
Claim 14
Dependent Claim
42 words
The system of claim 10; and a network for incrementing and decrementing said alignment indicator one unit for each bit shift of the word in said register provided by said justifier and operative to recycle the counting sequence of said alignment indicator.
Claim 15
Dependent Claim
18 words
The system of claim 13 wherein said justifier is responsive to only non-zero content in said alignment indicator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-24 | 1978-09-23 | 1979-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-24 | 1982-09-23 | 1983-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-24 | 1986-09-23 | 1987-03-25 | $7700.00 | Window Closed / Lapsed |