US3872431A
Expired / Lapsed
US
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Apparatus for detecting data bits and error bits in phase encoded data
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1973-12-10
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Granted: 1975-03-18
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Expires: 1993-12-10
Abstract
Abstract A plurality of binary-to-decimal converters, logic gates and inverters provide a signal to a first output terminal when at least one error occurs in a data character, provide a signal to a second output terminal when only one error occurs in the character and provide a signal to a third output terminal when at least two errors occur in the character.
Inventors
- 👤 Edward R Besenfelder
- 👤 Stanley I Friedman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 00:55
CPC Classifications
H; H03; H03M; H03M13/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
388 words
Apparatus for signaling the number of errors in data characters comprising: first, and second binary-to-decimal converters each having first, second, third and fourth input leads and first, second, third, fourth and fifth output leads; a third binary-to-decimal converter having first, second, third and fourth input leads and first, second, third and fourth output leads; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said third converter, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters; first and second logic gates each having first, second, third and fourth input leads and an output lead, said second, third, fourth and fifth output leads of said first converter each being connected to a corresponding one of said input leads of said first gate, said second, third, fourth and fifth output leads of said second converter each being connected to a corresponding one of said input leads of said second gate; third and fourth logic gates each having first and second input leads and an output lead, said first input lead of said third gate being coupled to said output lead of said first gate, said second input lead of said third gate being connected to said first output lead of said first converter, said first input lead of said fourth logic gate being coupled to said output lead of said second gate, said second input lead of said fourth gate being connected to said first output lead of said second converter; and a fifth logic gate having first, second, third, fourth, fifth and sixth input leads and an output lead, said output lead of said third gate being coupled to said first input lead of said fifth gate, said sixth input lead of said fifth gate being connected to said output lead of said fourth gate, said second, third, fourth and fifth output leads of said third converter each being coupled to a corresponding one of said second, third, fourth, and fifth input leads of said fifth logic gate, said output lead of said first gate being connected to said first input lead of said third converter, said output lead of said second gate being connected to said second input lead of said converter.
Claim 2
Dependent Claim
388 words
Apparatus for signaling the number of errors in data characters comprising: first, and second binary-to-decimal converters each having first, second, third and fourth input leads and first, second, third, fourth and fifth output leads; a third binary-to-decimal converter having first, second, third and fourth input leads and first, second, third and fourth output leads; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said third converter, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters; first and second logic gates each having first, second, third and fourth input leads and an output lead, said second, third, fourth and fifth output leads of said first converter each being connected to a corresponding one of said input leads of said first gate, said second, third, fourth and fifth output leads of said second converter each being connected to a corresponding one of said input leads of said second gate; third and fourth logic gates each having first and second input leads and an output lead, said first input lead of said third gate being coupled to said output lead of said first gate, said second input lead of said third gate being connected to said first output lead of said first converter, said first input lead of said fourth logic gate being coupled to said output lead of said second gate, said second input lead of said fourth gate being connected to said first output lead of said second converter; and a fifth logic gate having first, second, third, fourth, fifth and sixth input leads and an output lead, said output lead of said third gate being coupled to said first input lead of said fifth gate, said sixth input lead of said fifth gate being connected to said output lead of said fourth gate, said second, third, fourth and fifth output leads of said third converter each being coupled to a corresponding one of said second, third, fourth, and fifth input leads of said fifth logic gate, said output lead of said first gate being connected to said first input lead of said third converter, said output lead of said second gate being connected to said second input lead of said converter.
Claim 3
Dependent Claim
127 words
Apparatus for signaling a number of errors in data characters comprising: first and second binary-to-decimal converters each having first, second, third and fourth input leads and an output lead; a logic gate having first, second and third input leads and an output lead, said first input lead of said logic gate being connected to said output lead of said first converter, said second input lead of said logic gate being connected to said output lead of said second converter; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said logic gate, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters.
Claim 4
Dependent Claim
127 words
Apparatus for signaling a number of errors in data characters comprising: first and second binary-to-decimal converters each having first, second, third and fourth input leads and an output lead; a logic gate having first, second and third input leads and an output lead, said first input lead of said logic gate being connected to said output lead of said first converter, said second input lead of said logic gate being connected to said output lead of said second converter; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said logic gate, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters.
Claim 5
Dependent Claim
454 words
Apparatus for signaling the number of errors in data characters comprising: first, and second binary-to-decimal converters each having first, second, third and fourth input leads and first, second, third, fourth and fifth output leads; a third binary-to-decimal converter having first, second, third and fourth input leads and first, second, third and fourth output leads; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said third converter, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters; first and second logic gates each having first, second, third and fourth input leads and an output lead, said second, third, fourth and fifth output leads of said first converter each being connected to a corresponding one of said input leads of said first gate, said second, third, fourth and fifth output leads of said second converter each being connected to a corresponding one of said input leads of said second gate; third and fourth logic gates each having first and second input leads and an output lead, said first input lead of said third gate being coupled to said output lead of said first gate, said second input lead of said third gate being connected to said first output lead of said first converter, said first input lead of said fourth logic gate being coupled to said output lead of said second gate, said second input lead of said fourth gate being connected to said first output lead of said second converter; a fifth logic gate having first, second, third, fourth, fifth and sixth input leads and an output lead, said output lead of said third gate being coupled to said first input lead of said fifth gate, said sixth input lead of said fifth gate being connected to said output lead of said fourth gate, said second, third, fourth and fifth output leads of said third converter each being coupled to a corresponding one of said second, third, fourth, and fifth input leads of said fifth logic gate, said otput lead of said first gate being connected to said first input lead of said third converter, said output lead of said second gate being connected to said second input lead of said converter; and a sixth logic gate having first, second and third input leads and an output lead, said first input lead of said sixth gate being connected to said first output lead of said first converter, said second input lead of said gate being connected to said first output lead of said second converter, said input terminals being connected to said third input lead of said sixth gate.
Claim 6
Dependent Claim
454 words
Apparatus for signaling the number of errors in data characters comprising: first, and second binary-to-decimal converters each having first, second, third and fourth input leads and first, second, third, fourth and fifth output leads; a third binary-to-decimal converter having first, second, third and fourth input leads and first, second, third and fourth output leads; a plurality of signal input terminals, a first of said input terminals being connected to said third input lead of said third converter, each of the remainder of said input terminals being connected to a corresponding one of said input leads of said first and said second converters; first and second logic gates each having first, second, third and fourth input leads and an output lead, said second, third, fourth and fifth output leads of said first converter each being connected to a corresponding one of said input leads of said first gate, said second, third, fourth and fifth output leads of said second converter each being connected to a corresponding one of said input leads of said second gate; third and fourth logic gates each having first and second input leads and an output lead, said first input lead of said third gate being coupled to said output lead of said first gate, said second input lead of said third gate being connected to said first output lead of said first converter, said first input lead of said fourth logic gate being coupled to said output lead of said second gate, said second input lead of said fourth gate being connected to said first output lead of said second converter; a fifth logic gate having first, second, third, fourth, fifth and sixth input leads and an output lead, said output lead of said third gate being coupled to said first input lead of said fifth gate, said sixth input lead of said fifth gate being connected to said output lead of said fourth gate, said second, third, fourth and fifth output leads of said third converter each being coupled to a corresponding one of said second, third, fourth, and fifth input leads of said fifth logic gate, said otput lead of said first gate being connected to said first input lead of said third converter, said output lead of said second gate being connected to said second input lead of said converter; and a sixth logic gate having first, second and third input leads and an output lead, said first input lead of said sixth gate being connected to said first output lead of said first converter, said second input lead of said gate being connected to said first output lead of said second converter, said input terminals being connected to said third input lead of said sixth gate.
Claim 7
Dependent Claim
72 words
Apparatus for signaling the number of errors in data characters as defined in claim 3 including: a seventh logic gate having first and second input leads and an output lead, said first input lead of said seventh gate being connected to said output lead of said sixth gate; and an inverter, said inverter being connected between said output lead of said fifth gate and said second input lead of said seventh gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-17 | 1978-09-16 | 1979-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-17 | 1982-09-16 | 1983-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-17 | 1986-09-16 | 1987-03-18 | $7700.00 | Window Closed / Lapsed |