US3870970A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency dividing circuit
Assignee: Nippon Gakki Co Ltd
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Filing: 1974-01-28
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Granted: 1975-03-11
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Expires: 1994-01-28
Abstract
Abstract A waveform memory memorises a particular desired waveform as a sampled values at dotted time points. A ring counter driven by a voltage controlled oscillator reads the waveform memory to produce the memorized waveform signal. Ring counter cycle frequency fx is divided into fx/2n. An input signal frequency fi is divided into fi/2m. These fx/2n and fi/2m are compared with each other by a phase difference detector, whose output is applied back to the voltage controlled oscillator to bring the oscillator frequency to such a value that fx/2n Fi/2m, i.e. fx (n/m) fi. In this way, an output signal of a desired waveform and having a frequency fx which is of a ratio of any rational number n/m to the input signal frequency fi can be obtained.
Inventors
- 👤 Masanobu Chibana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 09:32
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G10; G10H; G10H7/00; G10H7/02; G10H7/04; H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
180 words
A frequency dividing circuit comprising a waveform memory memorizing a waveform, a voltage controlled oscillator, a counter connected to said voltage controlled oscillator to be driven thereby and connected to said waveform memory for reading out the memorized waveform, an input terminal for receiving an input signal, a 1/n-frequency divider connected to said counter for dividing the frequency of an output from said counter into 1/n, a 1/m-frequency divider connected to said input terminal for dividing the frequency of the input signal into 1/m, and a phase difference delector connected to said both frequency dividers for receiving the both frequency divided signals and connected to said voltage controlled oscillator for delivering an output voltage whenever a phase difference exists between the outputs from said 1/m and 1/n-frequency dividers, the oscillation frequency of said voltage-controlled oscillator being varied in accordance with the output voltage from said phase difference detector until there exists no difference, whereby the waveform memorized in said waveform memory is successively read out at a repetition frequency equal to an n/m times the frequency of the input signal.
Claim 2
Dependent Claim
180 words
A frequency dividing circuit comprising a waveform memory memorizing a waveform, a voltage controlled oscillator, a counter connected to said voltage controlled oscillator to be driven thereby and connected to said waveform memory for reading out the memorized waveform, an input terminal for receiving an input signal, a 1/n-frequency divider connected to said counter for dividing the frequency of an output from said counter into 1/n, a 1/m-frequency divider connected to said input terminal for dividing the frequency of the input signal into 1/m, and a phase difference delector connected to said both frequency dividers for receiving the both frequency divided signals and connected to said voltage controlled oscillator for delivering an output voltage whenever a phase difference exists between the outputs from said 1/m and 1/n-frequency dividers, the oscillation frequency of said voltage-controlled oscillator being varied in accordance with the output voltage from said phase difference detector until there exists no difference, whereby the waveform memorized in said waveform memory is successively read out at a repetition frequency equal to an n/m times the frequency of the input signal.
Claim 3
Dependent Claim
180 words
A frequency dividing circuit comprising a waveform memory memorizing a waveform, a voltage controlled oscillator, a counter connected to said voltage controlled oscillator to be driven thereby and connected to said waveform memory for reading out the memorized waveform, an input terminal for receiving an input signal, a 1/n-frequency divider connected to said counter for dividing the frequency of an output from said counter into 1/n, a 1/m-frequency divider connected to said input terminal for dividing the frequency of the input signal into 1/m, and a phase difference delector connected to said both frequency dividers for receiving the both frequency divided signals and connected to said voltage controlled oscillator for delivering an output voltage whenever a phase difference exists between the outputs from said 1/m and 1/n-frequency dividers, the oscillation frequency of said voltage-controlled oscillator being varied in accordance with the output voltage from said phase difference detector until there exists no difference, whereby the waveform memorized in said waveform memory is successively read out at a repetition frequency equal to an n/m times the frequency of the input signal.
Claim 4
Dependent Claim
180 words
A frequency dividing circuit comprising a waveform memory memorizing a waveform, a voltage controlled oscillator, a counter connected to said voltage controlled oscillator to be driven thereby and connected to said waveform memory for reading out the memorized waveform, an input terminal for receiving an input signal, a 1/n-frequency divider connected to said counter for dividing the frequency of an output from said counter into 1/n, a 1/m-frequency divider connected to said input terminal for dividing the frequency of the input signal into 1/m, and a phase difference delector connected to said both frequency dividers for receiving the both frequency divided signals and connected to said voltage controlled oscillator for delivering an output voltage whenever a phase difference exists between the outputs from said 1/m and 1/n-frequency dividers, the oscillation frequency of said voltage-controlled oscillator being varied in accordance with the output voltage from said phase difference detector until there exists no difference, whereby the waveform memorized in said waveform memory is successively read out at a repetition frequency equal to an n/m times the frequency of the input signal.
Claim 5
Dependent Claim
43 words
A frequency dividing circuit as set forth in claim 1 wherein a 1/2 -frequency divider is further provided between said 1/m-frequency divider and said phase difference detector, while another 1/2 -frequency divider is provided between said 1/n-frequency divider and said phase difference detector.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-03-10 | 1978-09-09 | 1979-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-03-10 | 1982-09-09 | 1983-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-03-10 | 1986-09-09 | 1987-03-11 | $7700.00 | Window Closed / Lapsed |