Data transmission systems and components therefor

Claim 2

A data transmission system comprising: a. a source of binary data signals of substantially rectangular waveform; b. a line driver circuit having a single input to which the output of the signal source is connected and having first and second outputs at which complementary output signals of trapezoidal waveform are developed in response to a signal of substantially rectangular waveform at said input; c. a balanced pair transmission line having a pair of inputs respectively connected to said first and second outputs of said line driver circuit, and having a pair of outputs; and d. a line receiver circuit having first and second inputs respectively connected to said pair of outputs of said transmission line; and having an output at which a signal of substantially rectangular waveform is developed in response to signals of trapezoidal waveform at said first and second inputs.

Claim 3

A data transmission system according to claim 1 wherein said driver circuit comprises a constant current source connected with said input so as to be active in one state only of the signal produced by said binary data signal source, and a capacitor connected with said current source to integrate the constant current and thereby produce an output current of trapezoidal waveform, and means for producing said complementary output signals of trapezoidal waveform in response to said output current.

Claim 4

A transmission system according to claim 2 wherein said means for producing said complementary signals comprises: a first complementary pair of transistors to whose bases are supplied potentials which vary with said output current of trapezoidal waveform and whose emitter-collector paths are connected across a supply voltage via respective collector and emitter circuit impedances; a second compplementary pair of transistors whose emitter-collector paths are connected in series across said supply voltage; a third complementary pair of transistors whose emitter-collector paths are connected in series across said supply voltage; a connection between the emitter of each of said first pair of transistors and the base of the transistor of said second pair of corresponding type; and a connection between the collector of each of said first pair of transistors and the base of the transistor of said third pair of opposite type; said first and second outputs being derived from the junction between said second pair of transistors and the junction between said third pair of transistors respectively.

Claim 5

A transmission system according to claim 3 wherein a respective temperature compensating diode is connected in series with each of said emitter and collector circuit impedances of said first pair of transistors.

Claim 6

A transmission system according to claim 2 wherein said line receiver circuit comprises first and second amplifying arrangements which exhibit hysteresis type input/output characteristics and whose inputs are respectively connected to said first and second inputs of the circuit; and a logic gate via which the outputs of the amplifying arrangements are connected to the output of the circuit.

Claim 7

A transmission system according to claim 5 wherein said line receiver circuit includes a comparator whose output is connected to at least one further input of said gate and whose input is connected with the outputs of said amplifying arrangements so as to inhibit said gate when the outputs of the amplifying arrangements are other than complementary with respect to a reference potential.

Claim 8

A transmission system according to claim 6 wherein said comparator comprises a pair of transistors, a common emitter resistor connected with said transistors; separate collector resistors connected with said transistors; a connection between the base of one of the transistors and a point on a potential divider connected between the outputs of the amplifying arrangements; and a connection between the base of the other transistor and a source of said reference potential.

Claim 9

A Transmission system according to claim 7 wherein each said amplifying arrangement comprises an operational amplifier having an inverting input and a non-inverting input; a connection between one of said inputs and a respective one of the inputs of the circuit; a resistance connected between said one input and ground, a resistance connected between the output of the operational amplifier and the other input of the operational amplifier; and a connection between said other input of the operational amplifier and junction between two resistances connected in series between a positive potential source and ground.