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US3868496A Expired / Lapsed US ⏱️ 0.0 years remaining

Control mechanism for producing random-like effects on textile materials

Assignee: Burlington Industries Inc
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Filing: 1973-05-15
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Granted: 1975-02-25
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Expires: 1993-05-15
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Abstract

Abstract A novel circuit, having a number of novel subcombinations thereof, for producing alternate on and off signals which can be used to control one or more clutches which, when activated, produce a slub on a yarn or thread or a space between slubs or for controlling any other suitable circuitry or equipment. This circuit produces an extremely long pseudo-random pattern of effect dispersion to give a true random-like appearance in cloth which is woven from such slub yarns or threads. The minimum length of the spaces and slubs can be independently set on switches which are manually accessible from the exterior of the device and also the ratio between minimum and maximum slub and space widths can be also set on other switches. The circuitry automatically causes the length of the slubs and spaces produced to vary within this range defined between the minimum and maximum values, choosing in a pseudo-random manner successive ones of a fixed number of divisions within that range. In the embodiment described below, that fixed number is 14 divisions between the minimum and maximum length of the slubs and spaces. The circuitry can further be caused to operate in a mode whereby the space or slub length remains constant and another mode in which each of the possible separations in the pseudo-random pattern is produced in succession but not necessarily in order. Similarly, the circuitry can be caused, by manual operation of a switch on the exterior of the device, to produce a slub or space of maximum or minimum length. This divisional application is particularly directed toward a counting circuit comprising a unique subcombination circuit with a first programable counter providing an output upon receipt of a given number of input signals, second and third programable counters receiving the output of the first counter, a flip-flop which shifts its output responsive to the outputs of the second and third counters and circuit logic responsive to the flip-flop for varying the program for the first counter to provide flexibility and permit production of slubs or spaces having a relatively long minimum length but relatively short maximum to maximum ratio.

Inventors

  • 👤 Charles D Pugh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 09:11
CPC Classifications
D; D01; D01H; D01H5/00; D01H5/18; D01H5/32; D01H5/36; H; H03; H03K; H03K3/00; H03K3/84

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 495 words
A counting circuit comprising: first counter means for providing at an output a first output signal upon each receipt of a given number of input signals, second counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a second output signal at an output upon each receipt of a given number of said first output signals, third counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a third output signal at an output upon each receipt of a predetermined number of said first output signals from said first counter means, flip-flop means connected to the output of said second counter means and to said enabling inputs of said second and third counters for shifting from a first to a second output condition, whenever said second output signal is provided by said second counter means and said flip-flop means is in said first condition, to provide an enabling input signal to said third counter means and no input enabling signal to said second counter means means connected to said flip-flop means for providing a signal for shifting said flip-flop means from said second to said first condition to provide an enabling input signal to said second counter means and no input enabling signal to said third counter means, first switch means connected to said second counter means for manually varying said given number of received first output signals upon receipt of which said second counter means provides one of said second output signals, second switch means connected to said third counter means for manually varying said predeterminEd number of received first output signals upon receipt of which said third counter means provides one of said third output signals, third switch means connected to said first counter means for manually varying said given number of input signals upon receipt of which said first counter means provides one of said first output signals, said third switch means having a plurality of positions and logic means connecting said third switch means to said first counter means and connected to said flip-flop means having, when enabled, a first condition, when said flip-flop means is in said first condition and said third switch means is set in a given position enabling said logic means, said first condition of said logic means causing said first counter means to produce said first output signal upon a first given number and a second condition, when said flip-flop means is in said second condition and said third switch means is set in that given position, and second condition of said logic means causing said first counter means to produce said first output signal upon a second given number different from said first given number.
Claim 2
Dependent Claim 495 words
A counting circuit comprising: first counter means for providing at an output a first output signal upon each receipt of a given number of input signals, second counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a second output signal at an output upon each receipt of a given number of said first output signals, third counter means connected to the output of said first counter means for receiving successive first output signals from said first counter means and providing, when an enabling input signal is provided at an enabling input, a third output signal at an output upon each receipt of a predetermined number of said first output signals from said first counter means, flip-flop means connected to the output of said second counter means and to said enabling inputs of said second and third counters for shifting from a first to a second output condition, whenever said second output signal is provided by said second counter means and said flip-flop means is in said first condition, to provide an enabling input signal to said third counter means and no input enabling signal to said second counter means means connected to said flip-flop means for providing a signal for shifting said flip-flop means from said second to said first condition to provide an enabling input signal to said second counter means and no input enabling signal to said third counter means, first switch means connected to said second counter means for manually varying said given number of received first output signals upon receipt of which said second counter means provides one of said second output signals, second switch means connected to said third counter means for manually varying said predeterminEd number of received first output signals upon receipt of which said third counter means provides one of said third output signals, third switch means connected to said first counter means for manually varying said given number of input signals upon receipt of which said first counter means provides one of said first output signals, said third switch means having a plurality of positions and logic means connecting said third switch means to said first counter means and connected to said flip-flop means having, when enabled, a first condition, when said flip-flop means is in said first condition and said third switch means is set in a given position enabling said logic means, said first condition of said logic means causing said first counter means to produce said first output signal upon a first given number and a second condition, when said flip-flop means is in said second condition and said third switch means is set in that given position, and second condition of said logic means causing said first counter means to produce said first output signal upon a second given number different from said first given number.
Claim 3
Dependent Claim 34 words
A counting circuit as in claim 1 wherein said logic means is enabled for certain positions of said first and second switches and is disabled for other positions of said first and second switches.

References Cited (Backward Citations)

US2558447A Cited
US2970763A Cited
US3750603A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-02-24 1978-08-26 1979-02-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-02-24 1982-08-26 1983-02-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-02-24 1986-08-26 1987-02-25 $7700.00 Window Closed / Lapsed

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