US3868480A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Event monitoring transceiver
Assignee: Telesciences Inc
•
Filing: 1974-01-24
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Granted: 1975-02-25
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Expires: 1994-01-24
Abstract
Abstract A data terminal utilizes a time division multiplexer to monitor traffic on 16 input lines and convert the information from parallel to serial form as a 16 word serial message, records the count data for each input line, and transmits accumulated count data over a phone line as a serial message of 16 sequential 16 bit words. The terminal has a Count Register and a Storage Register each of which is a 256 bit serial shift register. The Count Register is the active memory that stores the counts of the events as they occur while the Storage Register receives data from the Count Register periodically, and holds the data for transmission. The terminal operates in either cumulative or peak modes. In cumulative mode the count for each input line is transmitted when the terminal is interrogated. In peak mode the terminal stores and transmits for each line only the highest count which occurs during successive selected time intervals, such as an hour or half hour. In both modes data is transferred from the Count Register to a Comparator for comparison with data in the storage Register and the higher count is retained in the Storage Register. Incoming data continues to be received and the counts in the Count Register are incremented even during data transfer. One terminal input circuit may be utilized to count elapsed monitoring time in minutes. A traffic usage scanner pulse is provided to activate a usage scanner. Operation of the terminal is automatic, and data readout and subsequent clearing of the registers and counters is controlled by the remote interrogating unit.
Inventors
- 👤 Joseph M Murgio
- 👤 Lawrence J Pincus
- 👤 Guenter J Boehm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:30
CPC Classifications
H; H04; H04M; H04M3/00; H04M3/22; H04M3/36
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
532 words
Event monitoring transceiver apparatus comprising in combination a. a parallel to serial electrical signal input multiplexer having a plurality of independent input circuits adapted for connection to a plurality of independent input-signal conductors, and having an output circuit, b. an adder having first and second data input circuits and a data output circuit, said first data input circuit being operatively coupled to said multiplexer output circuit, c. a count register having a data input circuit operatively coupled to said adder data output circuit, and having a data output circuit operatively coupled to said adder second data input circuit, said count register receiving and holding event count data from said adder for each said multiplexer input circuit, d. a comparator having first and second data input circuits and a data output circuit, said first data input circuit being operatively coupled to said count register data output circuit, e. a storage register having a data input circuit operatively coupled to said comparator data output circuit, and having a data output circuit oeratively coupled to said comparator second data input circuit, said storage register receiving and holding event count data from said comparator for each input multiplexer input circuit, f. an output control circuit adapted for coupling to and for receiving transmission control signals from an output data transmission circuit, and being adapted in response to the receipt of such transmission control signals to generate and transmit output control signals to said storage register, g. output means having an input circuit operatively coupled to said output control circuit and to said storage register data output circuit, and having an output circuit adapted for coupling to said output transmission circuit, and h. timing control means continuously generating timing control signals and being operatively coupled to and sending timing control signals to all of said input multiplexer, adder, count register, comparator, storage register and output control circuit, whereby, under control of said timing means, 1. said plurality of multiplexer input circuits are each cyclically selectively singly sequentially operatively coupled to saiD multiplexer output circuit for a predetermined time interval to thereby deliver to said adder first input circuit a sequence of electrical signals corresponding to the signal condition at each of said multiplexer input circuits during the time interval that the particular input circuit is coupled to the said multiplexer output circuit, 2. said event count data in said Count register for each input multiplexer input circuit is circulated through and is incremented by said adder when the latter detects the occurrence of a valid event at the input circuit then selected, 3. said event count data in said count register and said event count data in said storage register are both read into said comparator and the event count data from each of said count and storage registers which is of larger magnitude for each input multiplexer input circuit is passed out of said comparator and back into said storage register, 4. and when said output control circuit is receiving transmission control signals from said output data transmission circuit, said event count data in said storage register is shifted out of said storage register and through said output means under control of said output control circuit.
Claim 2
Dependent Claim
532 words
Event monitoring transceiver apparatus comprising in combination a. a parallel to serial electrical signal input multiplexer having a plurality of independent input circuits adapted for connection to a plurality of independent input-signal conductors, and having an output circuit, b. an adder having first and second data input circuits and a data output circuit, said first data input circuit being operatively coupled to said multiplexer output circuit, c. a count register having a data input circuit operatively coupled to said adder data output circuit, and having a data output circuit operatively coupled to said adder second data input circuit, said count register receiving and holding event count data from said adder for each said multiplexer input circuit, d. a comparator having first and second data input circuits and a data output circuit, said first data input circuit being operatively coupled to said count register data output circuit, e. a storage register having a data input circuit operatively coupled to said comparator data output circuit, and having a data output circuit oeratively coupled to said comparator second data input circuit, said storage register receiving and holding event count data from said comparator for each input multiplexer input circuit, f. an output control circuit adapted for coupling to and for receiving transmission control signals from an output data transmission circuit, and being adapted in response to the receipt of such transmission control signals to generate and transmit output control signals to said storage register, g. output means having an input circuit operatively coupled to said output control circuit and to said storage register data output circuit, and having an output circuit adapted for coupling to said output transmission circuit, and h. timing control means continuously generating timing control signals and being operatively coupled to and sending timing control signals to all of said input multiplexer, adder, count register, comparator, storage register and output control circuit, whereby, under control of said timing means, 1. said plurality of multiplexer input circuits are each cyclically selectively singly sequentially operatively coupled to saiD multiplexer output circuit for a predetermined time interval to thereby deliver to said adder first input circuit a sequence of electrical signals corresponding to the signal condition at each of said multiplexer input circuits during the time interval that the particular input circuit is coupled to the said multiplexer output circuit, 2. said event count data in said Count register for each input multiplexer input circuit is circulated through and is incremented by said adder when the latter detects the occurrence of a valid event at the input circuit then selected, 3. said event count data in said count register and said event count data in said storage register are both read into said comparator and the event count data from each of said count and storage registers which is of larger magnitude for each input multiplexer input circuit is passed out of said comparator and back into said storage register, 4. and when said output control circuit is receiving transmission control signals from said output data transmission circuit, said event count data in said storage register is shifted out of said storage register and through said output means under control of said output control circuit.
Claim 3
Dependent Claim
92 words
Apparatus as set forth in claim 1 wherein said adder comprises event occurrence validation means operative to examine each multiplexer input circuit signal condition during a plurality of successive sequential cycles and determine and remember whether there is event data present or event data absent, and, effective responsive to a determination of event data present for at least two successive cycles followed by a determination of event data absent for at least two successive cycles at the same input circuit, to cause the event count for that input circuit to be incremented.
Claim 4
Dependent Claim
39 words
said event count data in said Count register for each input multiplexer input circuit is circulated through and is incremented by said adder when the latter detects the occurrence of a valid event at the input circuit then selected,
Claim 5
Dependent Claim
39 words
said event count data in said Count register for each input multiplexer input circuit is circulated through and is incremented by said adder when the latter detects the occurrence of a valid event at the input circuit then selected,
Claim 6
Dependent Claim
106 words
Apparatus as set forth in claim 1 wherein said adder comprises event occurrence validation means and event incrementing means, said validation means being operative to examine each multiplexer input circuit signal condition during a plurality of successive sequential cycles and determine and remember whether there is event data present or event data absent, and, effective responsive to a determination of event data present for at least two successive cycles followed by a determination of event data absent for at least two successive cycles at the same input circuit, to cause said event incrementing means to cause the event count for that input circuit to be incremented.
Claim 7
Dependent Claim
59 words
said event count data in said count register and said event count data in said storage register are both read into said comparator and the event count data from each of said count and storage registers which is of larger magnitude for each input multiplexer input circuit is passed out of said comparator and back into said storage register,
Claim 8
Dependent Claim
59 words
said event count data in said count register and said event count data in said storage register are both read into said comparator and the event count data from each of said count and storage registers which is of larger magnitude for each input multiplexer input circuit is passed out of said comparator and back into said storage register,
Claim 9
Dependent Claim
44 words
and when said output control circuit is receiving transmission control signals from said output data transmission circuit, said event count data in said storage register is shifted out of said storage register and through said output means under control of said output control circuit.
Claim 10
Dependent Claim
44 words
and when said output control circuit is receiving transmission control signals from said output data transmission circuit, said event count data in said storage register is shifted out of said storage register and through said output means under control of said output control circuit.
Claim 11
Dependent Claim
104 words
Apparatus as set forth in claim 1 wherein said comparator comprises event count comparator means and temporary storage means which latter receives simultaneously the event count data from each of said count and storage registers corresponding to the same multiplexer input circuit while said event count data from said count and storage registers is being compared for magnitude by said event count comparator means, said temporary storage means returning to said storage register under control of said event count comparator means the event count data of larger magnitude from either said count or storage registers and blocking the event count data of lesser magnitude.
Claim 12
Dependent Claim
123 words
Apparatus as set forth in claim 1 wherein said comparator comprises comparator input and output signal control means effective responsive to a first condition of a particular control signal from said timing control means to permit passage of data into said comparator input circuits and out of said comparator output circuit, and effective responsive to a second condition of said particular control signal from said timing control means to prevent passage of data into said comparator input circuits and out of said comparator output circuit, the time duration of said first condition of said particular control signal being equal to and coextensive with the sum of the time interval required for one complete input multiplexer cycle plus one of said predetermined time intervals.
Claim 13
Dependent Claim
104 words
Apparatus as set forth in claim 1 wherein said output control circUit comprises first control means effective responsive to receipt of a first transmission control signal from the output data transmission circuit to generate control signals operative to cause said event count data in said storage register to be continuously recirculated through said register and to the said input circuit of said output means, and operative to cause an output date transmission signal at the output circuit of said output means consisting of intervals of event count data signals from said storage register in alternation with intervals of signals from a different signal source.
Claim 14
Dependent Claim
154 words
Apparatus as set forth in claim 1 wherein said comparator comprises comparator input and output signal control means effective responsive to a first condition of a particular control signal from said timing control means to permit passage of data into said comparator input circuits and out of said comparator output circuit, and effective responsive to a second condition of said particular control signal from said timing control means to prevent passage of data into said comparator input circuits and out of said comparator output circuit, and wherein said output control circuit comprises first control means effective responsive to receipt of a first transmission control signal from the output data transmission circuit to generate control signals when said particular control signal from said timing control meams is characterized by its said second condition, said generated control signals being operative as long as generated to prevent said particular control signal from assuming its said first condition.
Claim 15
Dependent Claim
63 words
Apparatus as set forth in claim 3 wherein each said predetermined time interval during each cycle when each multiplexer input circuit is operatively coupled to said adder comprises a control data interval and a count data interval, said event occurrence validation means being operative only during said control data interval and said event incrementing means being operative only during said count data interval.
Claim 16
Dependent Claim
104 words
Apparatus as set forth in claim 3 wherein said comparator comprises event count comparator means and temporary storage means which latter receives simultaneously the event count data from each of said count and storage registers corresponding to the same multiplexer input circuit while said event count data from said count and storage registers is being compared for magnitude by said event count comparator means, said temporary storage means returning to said storage register under control of said event count comparator means the event count data of larger magnitude from either said count or storage registers and blocking the event count data of lesser magnitude.
Claim 17
Dependent Claim
154 words
Apparatus as set forth in claim 3 wherein said comparator comprises comparator input and output signal control means effective responsive to a first condition of a particular control signal from said timing control means to permit passage of data into said comparator input circuits and out of said comparator output circuit, and effective responsive to a second condition of said particular control signal from said timing control means to prevent passage of data into said comparator input circuits and out of said comparator output circuit, and wherein said output control circuit comprises first control means effective responsive to receipt of a first transmission control signal from the ouput data transmission circuit to generate control signals when said particular control signal from said timing control means is characterized by its said second condition, said generated control signals being operative as long as generated to prevent said particular control signal from assuming its said first condition.
Claim 18
Dependent Claim
116 words
Apparatus as set forth in claim 4 wherein each said predetermined time interval during each cycle when each multiplexer input circuit is coupled to the multiplexer output circuit comprises a control data interval and a count data interval, and wherein said comparator during the comparison cycle furthEr includes means effective to place in the control data interval associated with each multiplexer input circuit a pair of sequential recognition signals the first of which is operative during output data transmission to denote the end of the event count data for the previous multiplexer input circuit and the second of which is operative to denote the beginning of thee event count data for the next multiplexer input circuit.
Claim 19
Dependent Claim
88 words
Apparatus as set forth in claim 4 wherein said temporary storage means comprises a separate shift register for the event count data of each of said count and storage registers, said shift registers each introducing a data flow delay time equal to the aforesaid predetermined time interval during which each multiplexer input circuit is coupled to the multiplexer output circuit, whereby, one complete comparison cycle time consists of the sum of the time interval required for one complete input multiplexer cycle plus one of said predetermined time intervals.
Claim 20
Dependent Claim
104 words
Apparatus as set forth in claim 4 wherein said output control circuit comprises first control means effective responsive to receipt of a first transmission control signal from the output data transmission circuit to generate control signals operative to cause said event count data in said storage register to be continuously recirculated through said register and to the said input circuit of said output means, and operative to cause an output dats transmission signal at the output circuit of said output means consisting of intervals of event count data signals from said storage register in alternation with intervals of signals from a different signal source.
Claim 21
Dependent Claim
30 words
Apparatus as set forth in claim 6 wherein said output data transmission signal intervals of event count data signals and signals from a different signal source are of equal duration.
Claim 22
Dependent Claim
41 words
Apparatus as set forth in claim 6 wherein said output data transmission signal interval of event count data signals is equal to the time interval necessary to recirculate the event count data through the storage register an integral number of times.
Claim 23
Dependent Claim
35 words
Apparatus as set forth in claim 6 wherein said output data transmission signals which are signals from a different signal source are signals generated by signal generating means comprising part of said output control circuit
Claim 24
Dependent Claim
90 words
Apparatus as set forth in claim 6 wherein said generated control signals operative to cause recirculation of said event count data in said storage register comprise a first pulse train clock signal derived from said timing control means, wherein the incrementing and comparison operation of said adder and comparator are effected by a second pulse train clock signal and other timing signals derived from said timing control means, and wherein the repetition rate of said first clock signal is substantially slower than the repetition rate of said second clock signal.
Claim 25
Dependent Claim
62 words
Apparatus as set forth in claim 6 further including output control circuit additional control means operatively coupled to said first control means and effective responsive to receipt of a second transmission control signal from the output data transmission circuit to generate control signals operative to clear the event count data from the said storage and count registers and from the said adder.
Claim 26
Dependent Claim
54 words
Apparatus as set forth in claim 6 further including output control circuit second control means operatively coupled to said first control means and effective responsive to termination of the aforesaid first transmission control signal from the output data transmission circuit to cause said first control means to terminate the generation of said control signals.
Claim 27
Dependent Claim
39 words
Apparatus as set forth in claim 8 wherein said event occurrence validation means utilizes said count register as a memory to remember for each input circuit the sequence of occurrence of event data present and event data absent information.
Claim 28
Dependent Claim
88 words
Apparatus as set forth in claim 9 wherein said temporary storage means comprises a separatE shift register for the event count data of each of said count and storage registers, said shift registers each introducing a data flow delay time equal to the aforesaid predetermined time interval during which each multiplexer input circuit is coupled to the multiplexer output circuit, whereby, one complete comparison cycle time consists of the sum of the time interval required for one complete input multiplexer cycle plus one of said predetermined time intervals.
Claim 29
Dependent Claim
116 words
Apparatus as set forth in claim 9 wherein each said predetermined time interval during each cycle when each multiplexer input circuit is coupled to the multiplexer output circuit comprises a control data interval and a count data interval, and wherein said comparator during the comparison cycle further includes means effective to place in the control data interval associated with each multiplexer input circuit a pair of sequential recognition signals the first of which is operative during output data transmission to denote the end of the event count data for the previous multiplexer input circuit and the second of which is operative to denote the beginning of the event count data for the next multiplexer input circuit.
Claim 30
Dependent Claim
104 words
apparatus as set forth in claim 12 wherein said output control circuit comprises first control means effective responsive to receipt of a first transmission control signal from the output data transmission circuit to generate control signals operative to cause said event count data in said storage register to be continuously recirculated through said register and to the said input circuit of said output means, and operative to cause an output data transmission signal at the output circuit of said output means consisting of intervals of event count data signals from said storage register in alternation with intervals of signals from a different signal source.
Claim 31
Dependent Claim
100 words
Apparatus as set forth in claim 12 further including comparator input and output signal control means effective responsive to a first condition of a particular control signal from said timing control means to permit passage of data into and out of said comparator, and effective responsive to a second condition of said particular control signal from said timing control means to prevent passage of data into and out of said comparator, the time duration of said first condition of said particular control signal from said timing control means being equal to and coextensive with the aforesaid complete comparison cycle time.
Claim 32
Dependent Claim
41 words
Apparatus as set forth in claim 14 wherein said output data transmission signal interval of event count data signals is equal to the time interval necessary to recirculate the event count data through the storage register an integral number of times.
Claim 33
Dependent Claim
58 words
Apparatus as set forth in claim 19 wherein said first control means automatically terminates the generation of said control signals at such time as to cause the termination of storage register recirculation with the storage register event count data in proper alignment within the register to correspond to the alignment of event count data in the count register.
Claim 34
Dependent Claim
62 words
Apparatus as set forth in claim 23 further including output control circuit additional control means operatively coupled to said first control means and effective responsive to receipt of a second transmission control signal from the output data transmission circuit to generate control signals operative to clear the event count data from the said storage and count registers and from the said adder.
Claim 35
Dependent Claim
44 words
Apparatus as set forth in claim 24 wherein said storage register is in a static shift state during the time interval that said particular control signal exhibits its said second condition, and is in a dynamic shift state during the aforesaid comparison cycle time.
Claim 36
Dependent Claim
35 words
Apparatus as set forth in claim 25 wherein said output data transmission signals which are signals from a different signal source are signals generated by signal generating means comprising part of said output control circuit.
Claim 37
Dependent Claim
54 words
Apparatus as set forth in claim 29 further including output control circuit second control means operatively coupled to said first control means and effective responsive to termination of the aforesaid first transmission control signal from the output data transmission circuit to cause said first control means to terminate the generation of said control signals.
Claim 38
Dependent Claim
340 words
Event monitoring transceiver apparatus comprising in combination a. parallel to serial electrical signal input multiplexer means having an output circuit and a plurality of independent input circuits each cyclically selectively singly sequentially operatively coupled to said output circuit for a predetermined time interval to thereby deliver to said output circuit a sequence of electrical signals corresponding to the signal condition at each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, b. adder means and count register means, said adder means being operatively coupled to said count register means and to said multiplexer to receive the multiplexed output data from the latter and operative to increment the event data count in said count register for each multiplexer input circuit when the adder detects the occurrence of a valid event at the input circuit then selected, c. comparator means and storage register means, said comparator means being operatively coupled to said count register and to said storage register for receiving and comparing the event count data in each for each of said input circuits and thereafter transmitting the event count data of larger magnitude to said storage register means, d. output control circuit means and output means operatively coupled to each other and to said storage register means, said output cocntrol circuit means being adapted for coupling to and for receiving transmission control signals from an output data transmission circuit and being adapted in response to the receipt of such transmission control signals to generate and transmit output control signals to said storage register effective to shift said event count data out of said storage register means and through said output means under control of said output control circuit means, said output means having an output circuit adapted for coupling to said output transmission circuit, e. timing control means continuously generating timing control signals and operatively coupled to and sending timing control signals to all of said input multiplexer, adder, count register, comparator, storage register and output control circuit.
Claim 39
Dependent Claim
340 words
Event monitoring transceiver apparatus comprising in combination a. parallel to serial electrical signal input multiplexer means having an output circuit and a plurality of independent input circuits each cyclically selectively singly sequentially operatively coupled to said output circuit for a predetermined time interval to thereby deliver to said output circuit a sequence of electrical signals corresponding to the signal condition at each of said input circuits during the time interval that the particular selected input circuit is coupled to the said output circuit, b. adder means and count register means, said adder means being operatively coupled to said count register means and to said multiplexer to receive the multiplexed output data from the latter and operative to increment the event data count in said count register for each multiplexer input circuit when the adder detects the occurrence of a valid event at the input circuit then selected, c. comparator means and storage register means, said comparator means being operatively coupled to said count register and to said storage register for receiving and comparing the event count data in each for each of said input circuits and thereafter transmitting the event count data of larger magnitude to said storage register means, d. output control circuit means and output means operatively coupled to each other and to said storage register means, said output cocntrol circuit means being adapted for coupling to and for receiving transmission control signals from an output data transmission circuit and being adapted in response to the receipt of such transmission control signals to generate and transmit output control signals to said storage register effective to shift said event count data out of said storage register means and through said output means under control of said output control circuit means, said output means having an output circuit adapted for coupling to said output transmission circuit, e. timing control means continuously generating timing control signals and operatively coupled to and sending timing control signals to all of said input multiplexer, adder, count register, comparator, storage register and output control circuit.
References Cited (Backward Citations)
US3761618A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-24 | 1978-08-26 | 1979-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-24 | 1982-08-26 | 1983-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-24 | 1986-08-26 | 1987-02-25 | $7700.00 | Window Closed / Lapsed |