US3867693A
Expired / Lapsed
US
⏱️ 0.0 years remaining
LSI chip test probe contact integrity checking circuit
Assignee: International Business Machines Corp
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Filing: 1974-02-20
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Granted: 1975-02-18
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Expires: 1994-02-20
Abstract
Abstract LSI (large scale integration) semiconductor chips have two sets of Schottky diodes formed therein for assuring electrical contact between the chip voltage supply and I/O (input-output) signal contacts (or pads) and test probes. The diodes of one set form an AND circuit having the diode inputs coupled to respective chip input signal contacts. The other set of diodes have first terminals coupled to the output of the AND circuit, and have second terminals, each coupled to a respective chip output signal contact. When a plurality of test probes are brought into contact with the chip I/O and voltage supply contacts preliminary to running static and/or dynamic tests on the chip circuits, a selected signal level is applied concurrently to all probes which are connected to chip input signal contacts and to probes connected to the supply contacts. If there is good electrical contact between these probes and each of the input and supply contacts, a selected signal level (e.g. UP) appears at the output of the AND circuit. This output signal is then applied by the AND circuit (or an amplifier) to each of the chip output contacts via a respective diode in said other set, irrespective of the states of the functional logic on the chip. If good electrical contact exists between the chip output contacts and their respective probes, the UP output signal level will appear on all of the latter probes. Detection of the UP signal level on all of the latter probes indicates good contact between all probes and chip contacts. Once this is established, functional testing of the chip circuits can begin.
Inventors
- 👤 Sr George J Saxenmeyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:57
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2853
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
145 words
A method for determining contact integrity between voltage supply, input and output contacts of a semiconductor chip having logical circuits formed therein and coupled between said input and output contacts, and supply, input and output test probes adapted to be brought into electrical engagement with respective supply, input and output contacts, said method comprising the steps of applying voltage supply and input signals concurrently to the supply and input test probes, sensing said input signals by means of a logical AND circuit on the chip having its input connected to the input contacts and producing an output signal when said input signals are sensed concurrently by all AND circuit inputs, applying said output signal concurrently to all output contacts, sensing the output signals on the output test probes to determine whether or not all test probes are in electrical engagement with their respective chip contacts.
Claim 2
Independent Claim
145 words
A method for determining contact integrity between voltage supply, input and output contacts of a semiconductor chip having logical circuits formed therein and coupled between said input and output contacts, and supply, input and output test probes adapted to be brought into electrical engagement with respective supply, input and output contacts, said method comprising the steps of applying voltage supply and input signals concurrently to the supply and input test probes, sensing said input signals by means of a logical AND circuit on the chip having its input connected to the input contacts and producing an output signal when said input signals are sensed concurrently by all AND circuit inputs, applying said output signal concurrently to all output contacts, sensing the output signals on the output test probes to determine whether or not all test probes are in electrical engagement with their respective chip contacts.
Claim 3
Dependent Claim
250 words
The combination comprising, a large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals, a plurality of output contacts, and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts and responsive to input signals received by the input contacts for producing output signals at said output contacts, means for generating concurrently a desired input signal pattern for application to the chip input contacts, test probes connected to said generating means and adapted to be brought into engagement with respective ones of the input contacts for coupling said signal pattern to the input contacts, a logical AND circuit on the chip having an output and having a plurality of inputs, eacH input connected to a respective one of the input contacts for producing an output signal when the input signal pattern is applied concurrently to the input contacts, means on the chip coupling the output of the AND circuit to each of the output contacts for forcing the output contacts to a selected signal level when the AND circuit produces said output signal, additional test probes adapted to be brought into engagement with the output contacts, and means connected to the additional test probes for sensing the selected signal level on all of the output contacts concurrently, thereby determining contact integrity between said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes.
Claim 4
Dependent Claim
250 words
The combination comprising, a large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals, a plurality of output contacts, and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts and responsive to input signals received by the input contacts for producing output signals at said output contacts, means for generating concurrently a desired input signal pattern for application to the chip input contacts, test probes connected to said generating means and adapted to be brought into engagement with respective ones of the input contacts for coupling said signal pattern to the input contacts, a logical AND circuit on the chip having an output and having a plurality of inputs, eacH input connected to a respective one of the input contacts for producing an output signal when the input signal pattern is applied concurrently to the input contacts, means on the chip coupling the output of the AND circuit to each of the output contacts for forcing the output contacts to a selected signal level when the AND circuit produces said output signal, additional test probes adapted to be brought into engagement with the output contacts, and means connected to the additional test probes for sensing the selected signal level on all of the output contacts concurrently, thereby determining contact integrity between said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes.
Claim 5
Dependent Claim
182 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals, a plurality of output contacts, and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts, and responsive to input signals received by the input contacts for producing output signals at said output contacts, the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between the said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a logical AND circuit having an output and having a plurality of inputs, each input connected to a respective one of the input contacts, for producing an output signal when selected input signals are applied concurrently to the input contacts, and means coupling the output of the AND circuit to each of the output contacts for forcing the output contacts to a selected voltage level when the AND circuit produces said output signal.
Claim 6
Dependent Claim
182 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals, a plurality of output contacts, and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts, and responsive to input signals received by the input contacts for producing output signals at said output contacts, the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between the said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a logical AND circuit having an output and having a plurality of inputs, each input connected to a respective one of the input contacts, for producing an output signal when selected input signals are applied concurrently to the input contacts, and means coupling the output of the AND circuit to each of the output contacts for forcing the output contacts to a selected voltage level when the AND circuit produces said output signal.
Claim 7
Dependent Claim
34 words
The chip of claim 3 wherein the logical AND circuit comprises a plurality of Schottky diodes having a common base electrode forming the AND circuit output and having emitters forming the AND circuit inputs.
Claim 8
Dependent Claim
35 words
The chip of claim 4 wherein the last-mentioned means comprises an additional plurality of Schottky diodes having a common base electrode coupled to the AND circuit output and having emitters coupled to the output contacts.
Claim 9
Dependent Claim
180 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals; a plurality of output contacts; a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts and responsive to input signals received by the input contacts for producing output signals at said output contacts; the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between the input contacts and respective test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a logic AND circuit having an output and having a plurality of inputs, each input connected to a respective one of the input contacts, for producing an output signal when selected input signals are applied concurrently to the input contacts; and means coupling the output of the AND circuit to an output contact for forcing the output contact to a selected voltage level when the AND circuit produces said output signal.
Claim 10
Dependent Claim
180 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals; a plurality of output contacts; a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts and responsive to input signals received by the input contacts for producing output signals at said output contacts; the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between the input contacts and respective test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a logic AND circuit having an output and having a plurality of inputs, each input connected to a respective one of the input contacts, for producing an output signal when selected input signals are applied concurrently to the input contacts; and means coupling the output of the AND circuit to an output contact for forcing the output contact to a selected voltage level when the AND circuit produces said output signal.
Claim 11
Dependent Claim
237 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals; a plurality of output contacts; and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts, and responsive to input signals received by the input contacts for producIng output signals at said output contacts; the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a first plurality of Schottky barrier diodes connected to form a logic AND circuit, each diode having an input terminal coupled to a respective one of the input contacts and having an output terminal coupled in common with the output terminals of the remaining diodes, a second plurality of Schottky barrier diodes, each second diode having one terminal coupled to a respective one of the output contacts and having another terminal coupled in common with the other terminals of the remaining second diodes to the output terminals of the first diodes, and said first diodes adapted to respond to a signal of selected voltage applied concurrently to all of the input contacts for causing the second diodes to force all of the output contacts to a selected voltage level.
Claim 12
Dependent Claim
237 words
A large scale integration semiconductor chip having a plurality of input contacts adapted to receive input signals; a plurality of output contacts; and a plurality of logic circuits including inputs connected to respective ones of the input contacts, including outputs connected to respective ones of the output contacts, and responsive to input signals received by the input contacts for producIng output signals at said output contacts; the combination with said input contacts, output contacts and logic circuits of means on the chip for determining contact integrity concurrently between said contacts and test probes preliminary to electrical testing of said logic circuits via the test probes, said means comprising a first plurality of Schottky barrier diodes connected to form a logic AND circuit, each diode having an input terminal coupled to a respective one of the input contacts and having an output terminal coupled in common with the output terminals of the remaining diodes, a second plurality of Schottky barrier diodes, each second diode having one terminal coupled to a respective one of the output contacts and having another terminal coupled in common with the other terminals of the remaining second diodes to the output terminals of the first diodes, and said first diodes adapted to respond to a signal of selected voltage applied concurrently to all of the input contacts for causing the second diodes to force all of the output contacts to a selected voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-17 | 1978-08-19 | 1979-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-17 | 1982-08-19 | 1983-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-17 | 1986-08-19 | 1987-02-18 | $7700.00 | Window Closed / Lapsed |