Analog speed detector

Claim 2

A speed detector for producing from an input signal having a repetition rate related to the actual speed of a moving vehicle an analog output signal indicative of the speed of said vehicle, comprising, in combination: means responsive to said input signal for generating a control signal defining first and second operating periods; error detection means for generating an error signal, said error signal progressively changing during said first operating period from a first predetermined initial voltage level to a final voltage level, said final voltage level being dependent on the duration of said first operation period and on the rate at which said error signal progressively changes, and remaining at said final voltage level during at least a portion of said second operation period; integrator means for developing an output signal having a level dependent on the amplitude and polarity of momentarily applied signals; means for applying said error signal at said final voltage level to said integrator means during at least a portion of said second operating period; and means responsive to the output signal developed by said integrator means for controlling the rate at which said error signal progressively changes during said first operating period such that said output signal developed by said storage means comprises an analog signal indicative of the speed of said vehicle.

Claim 3

A speed detector as defined in claim 1 wherein said control signal is a square-wave, said first and second operating cycles comprising alternate half-cycles thereof.

Claim 4

A speed detector as defined in claim 2 which further includes means responsive to said square-wave control signal for generating a control pulse of predetermined duration, and wherein said error detection means are responsive to said control pulse in generating said error signal.

Claim 5

A speed detector as defined in claim 3 which further includes compensating means responsive to the speed of said vehicle for proportioning the effect of said error signal on said output voltage to the speed of said vehicle.

Claim 6

A speed detector as defined in claim 4 wherein said compensating means comprise means for generating a gating pulse width-dependent on the speed of said vehicle, and transfer means serially disposed between said error detector and said storage means and responsive to said gating pulse for controlling the portion of said error signal applied to said storage means.

Claim 7

A speed detector for producing from an electrical speed-indicating input signal having a repetition rate related to the actual speed of a moving vehicle an analog output signal indicative of the speed of said vehicle, comprising, in combination: means responsive to said speed-indicating input signal for generating a control signal defining first and second operating periods; an error integrating capacitor; charging means for establishing an initial charge condition of predetermined magnitude and polarity on said capacitor prior to sAid first operating period; discharging means for applying a predetermined current of opposite polarity to said capacitor during said first operating period, the voltage across said capacitor progressing from a predetermined initial voltage level to a final voltage level at the end of said operating period, said final voltage level being dependent on the duration of said period; storage means for developing an analog output signal representative of the amplitude of momentarily applied signals; transfer means for coupling said capacitor to said storage means during at least a portion of said second operating period to apply at least a portion of the final voltage existing across said capacitor thereto; and means responsive to the analog output signal developed by said storage means for controlling the charging rate of said capacitor during said first operating period such that said output signal developed by said storage means comprises an analog output signal indicative of the speed of said vehicle.

Claim 8

A speed detector for producing from an electrical speed-indicating input signal having a repetition rate related to the actual speed of a moving vehicle an analog output signal indicative of the speed of said vehicle, comprising, in combination: means responsive to said speed-indicating input signal for generating a control signal defining first and second operating periods; an error integrating capacitor; charging means for establishing an initial charge condition of predetermined magnitude and polarity on said capacitor prior to sAid first operating period; discharging means for applying a predetermined current of opposite polarity to said capacitor during said first operating period, the voltage across said capacitor progressing from a predetermined initial voltage level to a final voltage level at the end of said operating period, said final voltage level being dependent on the duration of said period; storage means for developing an analog output signal representative of the amplitude of momentarily applied signals; transfer means for coupling said capacitor to said storage means during at least a portion of said second operating period to apply at least a portion of the final voltage existing across said capacitor thereto; and means responsive to the analog output signal developed by said storage means for controlling the charging rate of said capacitor during said first operating period such that said output signal developed by said storage means comprises an analog output signal indicative of the speed of said vehicle.

Claim 9

A speed detector as defined in claim 6 wherein said control signal is a square-wave signal and said first and second operating periods correspond to alternate half-cycles thereof.

Claim 10

A speed detector as defined in claim 7 wherein said means for coupling said capacitor to said storage means are responsive to and function only during a portion of the second half-cycle of said square-wave.

Claim 11

A speed detector as defined in claim 8 which further includes means responsive to the transition of said square-wave control signal from its first half-cycle to its second half-cycle for producing a control pulse having a predetermined duration, less than said second operating period, and wherein said charging and discharging means are rendered inoperative by said control pulse.

Claim 12

A speed detector as defined in claim 6 which further includes compensating means responsive to the speed of said vehicle for proportioning the effect of said error signal on said output voltage to the speed of said vehicle.

Claim 13

A speed detector as defined in claim 10 wherein said compensating means comprise means for generating a gating pulse width-dependent of the speed of said vehicle, and transfer means serially disposed between said error detector and said storage means and responsive to said gating pulse for controlling the portion of said error signal applied to said storage means.

Claim 14

A speed detector as defined in claim 6 which further comprises an inverting amplifier having its input coupled to one terminal of said error integrating capacitor and its output coupled to the other terminal of said capacitor to form an error integrating circuit, and wherein said charging means and discharging means are coupled to said input terminal to alternately cause current flow thereto in opposite directions.

Claim 15

A speed detector as defined in claim 12 wherein said charging means include a first avalanche diode coupled between the output of said amplifier and said input for opposing further charging of said capacitor beyond said initial charge condition.

Claim 16

A speed detector as defined in claim 13 wherein said discharging means include a second avalanche diode coupled between the output of said amplifier and said input for opposing discharge of said capacitor beyond a predetermined terminal charge condition.

Claim 17

A speed detector as defined in claim 6 which further comprises an amplifier for amplifying the output of said storage means to develop said analog output signal.

Claim 18

A speed detector for producing from an input signal having a frequency related to the actual speed of a moving vehicle, an output signal indicative of the error between the actual speed of said vehicle, and a predetermined nominal speed, comprising, in combination: means responsive to said speed-indicating signal for generating a control signal defining first and second operating periods; error detection means for generating an error signal, said error signal progressively changing during sAid first operating period from a predetermined initial voltage level to a final voltage level dependent on the duration of said first operating period, and remaining thereat during at least a portion of said second operating period; means for controlling the rate of progression of said error signal such that said final error voltage level comprises a predetermined reference voltage level when said vehicle is operating at a predetermined nominal speed; storage means for developing an output signal representative of the amplitude of signals periodically applied thereto; and means for applying said error signal existing at the end of said first operating period to said storage means during at least a portion of said second operating period such that said output signal is indicative of the error between said actual speed and said nominal speed.

Claim 19

A speed detector for producing from an input signal having a frequency related to the actual speed of a moving vehicle, an output signal indicative of the error between the actual speed of said vehicle, and a predetermined nominal speed, comprising, in combination: means responsive to said speed-indicating signal for generating a control signal defining first and second operating periods; error detection means for generating an error signal, said error signal progressively changing during sAid first operating period from a predetermined initial voltage level to a final voltage level dependent on the duration of said first operating period, and remaining thereat during at least a portion of said second operating period; means for controlling the rate of progression of said error signal such that said final error voltage level comprises a predetermined reference voltage level when said vehicle is operating at a predetermined nominal speed; storage means for developing an output signal representative of the amplitude of signals periodically applied thereto; and means for applying said error signal existing at the end of said first operating period to said storage means during at least a portion of said second operating period such that said output signal is indicative of the error between said actual speed and said nominal speed.