Three phase jump encoder and decoder

Claim 2

Apparatus for encoding binary data comprising: storage means for storing at least two successive bits of said data; clock means for entering said data into said storage means and for establishing the bit time interval of the encoded data, carrier signal generating means, means for shifting the phase of the carrier signal by a first or second predetermined phase angle, comparator means responsive to said clock means and to the state of said successive bits of data for detecting when said successive bits of data form the two bit configuration 11 or 00, means responsive to the detection of the two bit configuration 11 for controlling said phase shifting means to cause said carrier signal to be shifted by said first predetermined phase angle and responsive to the detection of the two bit configuration 00 for causing said phase shifting means to shift the phase of saiD carrier by said second predetermined phase angle, means for inhibiting said comparator means for one bit time interval following detection of the two bit configuration 11 or 00.

Claim 3

Apparatus for encoding binary data comprising: storage means for storing at least first, second, and third successive bits of said data, clock means for entering said data into said storage means and for establishing the bit time interval of the encoded data, carrier signal generating means, means for shifting the phase of said carrier signal by a first, second or third predetermined phase angle, comparator means responsive to said clock means and to the state of said first, second and third bits for detecting the two bit configuration 11 or 00 or the three bit configuration 010 or 101, means responsive to said comparator means for controlling said phase shifting means to shift the phase of said carrier signal by said first predetermined phase angle in response to detection of the two bit configuration 11 and by said second phase angle in response to detection of the two bit configuration 00 and by said third predetermined phase angle in response to detection of the three bit configuration 010 or 101, means for inhibiting said comparator means for one bit time following detection of either of said two bit configurations or either of said three bit configurations.

Claim 4

The apparatus defined in claim 2 wherein said first predetermined phase angle is 180*, said second predetermined phase angle is 300*, and said third predetermined phase angle is 60*.

Claim 5

Apparatus for encoding binary data comprising: data storage means for storing at least first, second, and third successive bits of data, carrier signal generating means for producing six output signals separated from each other by a 60* phase angle, first logic gate means for detecting when said first and second bits of data are 11, second logic gate means for detecting when said first and second bits of data are 00, third logic gate means for detecting when said first, second, and third bits of data are 010 or 101, means for inhibiting said first, second, and third logic gate means for one bit time following detection of either of said two or three bit configurations, phase selection logic means responsive to said first, second, and third logic gate means for selecting the appropriate output of said phase generating means to shift the phase of the carrier signal by 180* upon detection of the two bit configuration 11 and to shift the phase of the carrier signal by 300* in response to detection of the two bit configuration 00 and to shift the phase of the carrier signal by a phase angle of 60* in response to the detection of either of the three bit configurations 101 or 010.

Claim 6

Apparatus for decoding a phase jump encoded signal comprising: phase angle detector means for detecting the phase angle of the encoded data, storage means responsive to said detector means for storing the present and previous phase angle of the encoded data, logic means responsive to the previous and present phase angle of said encoded data for developing a first control pulse train containing pulses representing a phase angle jump of the encoded data of 180*, second logic means responsive to the previous and present phase angle of said encoded data for developing a second control pulse train containing pulses representing a phase angle jump of the encoded data of 300*, formulation register means, means responsive to said first control pulse train for formulating in said register means a bit stream comprising the two bit configuration 11 followed by an alternate 01 bit pattern of length dependent on the elapsed bit time interval between a previous pulse in one of said first or second coNtrol pulse trains, means responsive to said second control pulse train for formulating in said register means a bit stream comprising the two bit configuration 00 followed by an alternate 10 bit pattern of length dependent on the elapsed bit time since a previous pulse in one of said first or second control pulse trains.

Claim 7

Apparatus for encoding binary data comprising: clocking means for forming a plurality of bit cells of substantially uniform time durations, complementary bit pair detection means responsive to the binary data and to the clocking means for comparing the state of each bit of said data with the state of the succeeding bit of said data to produce first control pulses upon detection of discrete pairs of adjacent bits of a predetermined bit pair configuration, and produce second control pulses upon detection of discrete pairs of adjacent bits which are the complement of said predetermined bit pair configuration, controlled means for providing an output carrier signal which may be shifted from its existing phase by a first or second predetermined phase angle, said controlled means responding to said first control pulses by shifting the existing phase of said carrier signal by said first predetermined phase angle at the beginning of the first of the two bit cells containing said predetermined bit pair configuration, and responding to said second control pulses by shifting the existing phase of said carrier signal by said second predetermined phase angle at the beginning of the first of the two bit cells containing the complement of said two bit configuration, said controlled means maintaining the existing phase of the carrier signal during the bit cells preceding and following the bit cell in which the shifting of the carrier signal occurs.

Claim 8

Apparatus for encoding binary data comprising: clocking means for forming a plurality of bit cells of substantially uniform time durations, carrier signal generating means for generating a carrier signal, logic means responsive to said binary data and to said clocking means for shifting the phase of said carrier signal by a first or second predetermined phase angle such that one bit of binary information is communicated in each of said bit cells, said logic means responding to pairs of adjacent bits forming one of the four possible two bit configurations by shifting the existing phase of said carrier signal by said first predetermined phase angle during one of the corresponding pairs of bit cells containing said pair of adjacent bits except where a phase shift has occurred in the bit cell preceding said pair of bit cells, said logic means responding to pairs of adjacent bits forming the complement of said one of the four possible two bit configurations by shifting the existing phase of said carrier signal by said second predetermined phase angle during one of the corresponding pair of bit cells containing said complement except where a phase shift has occurred in the bit cell preceding said pair of bit cells containing said complement, said logic means maintaining the existing phase of the carrier signal during the bit cells preceding and following the bit cell in which the shifting of the carrier signal occurs.

Claim 9

Apparatus for encoding binary data comprising: clocking means for forming a plurality of bit cells of substantially uniform time durations, carrier signal generating means for generating a carrier signal, logic means responsive to said binary data and to said clocking means for shifting the phase of said carrier signal by first, second, or third predetermined phase angles such that one bit of binary information is communicated in each of said bit cells, said logic means responding to adjacent bits of binary data which are 11 by shifting the phase of said carrier signal by said first predetermined phase angle at the beginning of the first of the two bit cells containing the adjacent bits which are 11 except where the pair of bit ceLls are preceded by a bit cell in which a phase shift has occurred and responding to those bits of binary data which are 00 by shifting the phase of said carrier signal by said second predetermined phase angle at the beginning of the first of the two bit cells containing the pair of adjacent bits which are 00 except where said last mentioned pair of bit cells are immediately preceded by a bit cell in which a phase shift has occurred, and responding to those of said bits of binary data which form the three bit configurations of either 101 or 010 by shifting the phase of said carrier signal by said third predetermined phase angle at the beginning of the first of the three bit cells containing said three bit configurations except where the said three bit cells are immediately preceded by a bit cell in which a phase shift has occurred.

Claim 10

Apparatus for processing binary data comprising: clocking means for forming a plurality of bit cells of substantially uniform time durations, carrier signal generating means for generating a carrier signal, logic means responsive to said binary data and to said clocking means for shifting the phase of said carrier signal by first, second, or third predetermined phase angles such that one bit of binary information is communicated in each of said bit cells, said logic means responding to adjacent bits of binary data which are 11 by shifting the phase of said carrier signal by said first predetermined phase angle at the beginning of the first of the two bit cells containing the adjacent bits which are 11 except where the pair of bit cells are preceded by a bit cell in which a phase shift has occurred and responding to those bits of binary data which are 00 by shifting the phase of said carrier signal by said second predetermined phase angle at the beginning of the first of the two bit cells containing the pair of adjacent bits which are 00 except where said last mentioned pair of bit cells are immediately preceded by a bit cell in which a phase shift has occurred, and responding to those of said bits of binary data which form the three bit configurations of either 101 or 010 by shifting the phase of said carrier signal by said third predetermined phase angle at the beginning of the first of the three bit cells containing said three bit configurations except where the said three bit cells are immediately preceded by a bit cell in which a phase shift has occurred, means for decoding said binary information from said carrier signal by responding to said phase shifts to detect the boundaries of said bit cells, said decoding means responding to phase shifts of said carrier signal of said first predetermined phase angle to register a 1 in each such bit cell and in the bit cell following such bit cell and responding to those phase shifts of said second predetermined phase angle to register a 0 in each such bit cell and in the bit cell following such bit cell, said decoding means registering either a 1 or a 0 in the remaining bit cells so that no additional pairs of adjacent like bits are registered in the remaining bit cells and the bit registered in the bit cell which precedes a bit cell containing a phase shift of said first or second predetermined phase angles is the complement of the bit registered in the bit cell in which the phase shift occurs.

Claim 11

Apparatus for encoding binary data comprising: clock means for forming a plurality of bit cells of substantially uniform time durations, carrier signal generating means for generating a carrier signal, logic means responsive to the state of adjacent bits of said binary data and to said clock means for shifting the phase of said carrier signal by a first, second, or third predetermined phase angle, said logic means responding to each of a first pair of adjacent uncoded bits of said binary data forming the two bit configuration 11 by shifting the existing phase of said carrier signaL by said first predetermined phase angle during a selected one of the bit cells containing said first pair of bits to identify the state of the two adjacent bits of data, said logic means responding to each of a second pair of adjacent uncoded bits of said binary data forming the two bit configuration 00 by shifting the existing phase of said carrier signal by said second predetermined phase angle during a selected one of the bit cells containing said second pair of bits to identify the state of the two adjacent bits of data, said logic means responding to each of a third pair of adjacent uncoded bits of said binary data forming one of the two possible two bit configurations having complementary bits, by shifting the phase of said carrier signal by said third predetermined phase angle during a selected one of the two bit cells containing said third pair of bits to identify the state of the two adjacent bits of data.

Claim 12

The apparatus defined in claim 10 wherein said encoder logic means responds to those uncoded bits of said data of said other binary character which are followed by a bit of said other binary character by shifting the phase of said carrier signal by a third predetermined phase angle.

Claim 13

The apparatus defined in claim 10 wherein said selected one of the bit cells containing said adjacent bits is the bit cell containing the first of the two adjacent bits.

Claim 14

The apparatus defined in claim 12 wherein said one of said two possible two bit configurations is 10.

Claim 15

The apparatus defined in claim 12 wherein said one of said two possible two bit configurations is 01.

Claim 16

Apparatus for encoding binary data and subsequently decoding the data comprising: clock means for forming a plurality of bit cells of substantially uniform time durations, carrier signal generating means for generating a carrier signal, logic means responsive to said binary data and to said clock means for shifting the phase of said carrier signal by a first or second predetermined phase angle at the beginning of selected ones of the bit cells containing the bits of said data to thereby code both the binary character of the bit and the selected ones of the bit cells and the bit in the bit cell immediately following said selected bit cells, said logic means responding to those of said bits of said data of one binary character by shifting the phase of said carrier signal at the beginning of each corresponding bit cell by said first or second predetermined phase angle depending upon whether said corresponding bit cell is immediately followed by a bit cell containing a bit of said one binary character or the other binary character respectively, decoder logic means responsive to said carrier signal for registering said one binary character in each bit cell containing a phase shift of said first or second predetermined phase angle and registering said one or said other binary character in the following bit cell depending upon whether the phase shift is of said first or second predetermined phase angle, said decoder logic means registering said other binary character in each of the remaining bit cells.