US3866221A
Expired / Lapsed
US
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Beacon decoder system
Assignee: Individual
•
Filing: 1973-09-17
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Granted: 1975-02-11
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Expires: 1993-09-17
Abstract
Abstract A decoder system useful in a radar beacon system for facilitating discrimination between reply signals occurring in near time coincidence. For each pair of framing pulses appearing at the ends of a delay line, an AND gate sends a strobe pulse to a plurality of NAND gates to thereby read out data pulses occurring between the framing pulses into a register for temporary storage. The register is adapted to accept or reject the data pulses dependent upon whether they have a width equal to that of their associated strobe pulse. The data bits thus stored in the register are transferred into other suitable code registers in controlled sequence. The disclosed beacon decoder is also capable of detecting the condition of at least two reply signals overlapping in time so that some of their data-pulse positions occur in exact time coincidence. Even in such overlapping condition, the decoder can derive range information from the reply signals while preventing readout of incorrect code information.
Inventors
- 👤 Mitsuo Hikosaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:50
CPC Classifications
G; G01; G01S; G01S13/00; G01S13/74; G01S13/76; G01S13/78; G01S13/781; G01S13/784
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
250 words
A decoder system for use in a communication system of the character in which the format of a signal is comprised of a first and second framing pulses spaced in time by a fixed interval, said signal format additionally containing a plurality of data bits represented by the presence and absence of pulses, each occurring during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, said decoder system being useful in discriminating between signals occurring in near time coincidence and comprising: converter means for converting said signals from serial to parallel form, said converter means having a plurality of output taps each associated with one of said data bits provided between said framing pulses; coincidence means, connected to said converter means to detect the coincidence of the first and second framing pulses of each signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said converter means output taps, said gating means being responsive to said coincidence signal to read out said data pulses from said converter means; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether it has a width equal to that of said coincidence signal.
Claim 2
Dependent Claim
250 words
A decoder system for use in a communication system of the character in which the format of a signal is comprised of a first and second framing pulses spaced in time by a fixed interval, said signal format additionally containing a plurality of data bits represented by the presence and absence of pulses, each occurring during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, said decoder system being useful in discriminating between signals occurring in near time coincidence and comprising: converter means for converting said signals from serial to parallel form, said converter means having a plurality of output taps each associated with one of said data bits provided between said framing pulses; coincidence means, connected to said converter means to detect the coincidence of the first and second framing pulses of each signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said converter means output taps, said gating means being responsive to said coincidence signal to read out said data pulses from said converter means; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether it has a width equal to that of said coincidence signal.
Claim 3
Dependent Claim
123 words
A system as defined in claim 1, further comprising: a plurality of control means, each associated with one of said signals, each of said control means being responsive to only its associated coincidence signal for producing a transfer signal; a plurality of groups of gating means, each of said gating means in each group being connected to one of said memory means data bins and connected together to its associated control means to read out said data bits from said memory means in response to said transfer signal; and a plurality of code memory means, each comprising a plurality of data bins, each of said data bins being connected to its associated gating means to receive said data bit from said memory means.
Claim 4
Dependent Claim
81 words
A system as defined in claim 2, further comprising: detecting means, connected to said coincidence means to detect the condition of at least two signals overlapping in time so that some of their time slots occur in exact time coincidence; and clear signal generating means, connected to said detecting means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.
Claim 5
Dependent Claim
53 words
A system as defined in claim 3, further comprising: reset signal generating means, connected to said detecting means to generate a reset signal in response to the occurrence of said overlapping condition; said control means being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.
Claim 6
Dependent Claim
251 words
A decoder system useful in a radar beacon system for discriminating between reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: delay means for converting said reply signals from serial to parallel form, said delay means having a time delay equal to the fixed time interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay means; coincidence means, connected to said delay means to detect the coincidence of the first and second framing pulses of each reply signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said delay means output taps, said gating means being responsive to said coincidence signal to read out said data pulses appearing at said output taps; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse from said delay means with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.
Claim 7
Dependent Claim
251 words
A decoder system useful in a radar beacon system for discriminating between reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: delay means for converting said reply signals from serial to parallel form, said delay means having a time delay equal to the fixed time interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay means; coincidence means, connected to said delay means to detect the coincidence of the first and second framing pulses of each reply signal and connected to produce a coincidence signal when such coincidence is detected; a plurality of gating means, each connected to one of said delay means output taps, said gating means being responsive to said coincidence signal to read out said data pulses appearing at said output taps; and memory means comprising a plurality of data bins each for storing one of said data bits, said memory means including comparator means for comparing the width of each data pulse from said delay means with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.
Claim 8
Dependent Claim
175 words
A system as defined in claim 5, in which each of said memory means data bins comprises: a first binary storage device, connected to the output of its associated gating means to set said first binary storage device upon receipt of each data pulse; a first gate, connected to the outputs of said associated gating means and of said coincidence means to enable said first gate when said data pulse does not have a width equal to that of said coincidence signAl; a second storage device, connected to the output of said first gate to set said storage device when said first gate is enabled; and a second gate, connected to the outputs of said second storage device and of said coincidence means to enable said second gate when said second storage device is in its set state and the trailing edge of said coincidence signal is detected, the output of said second gate being connected to said first and second storage devices to reset the same in response to said second gate being enabled.
Claim 9
Dependent Claim
133 words
A system as defined in claim 5, further comprising: a plurality of control circuits, each associated with one of said reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal; a plurality of groups of gating means, each of said gating means in every group being connected to one of said memory means data bins and connected together to its associated control circuit to read out the data bit stored in said memory means in response to said transfer signal; and a plurality of code memory means, each comprising a plurality of data bins, each of said code memory data bins being connected to its associated gating means to receive the data bit from said memory means in response to said transfer signal.
Claim 10
Dependent Claim
85 words
A system as defined in claim 7, in which each of said control circuits is responsive to its associated coincidence signal to produce another transfer signal; a plurality of groups of another gating means, each of said another gating means in every group being connected to one of said data bins of its associated code memory means and connected together to its associated control circuit to read out the data bit stored in its associated code memory means in response to said another transfer signal.
Claim 11
Dependent Claim
22 words
A system as defined in claim 8, in which said another transfer signal is utilized as a radar echo to determine range.
Claim 12
Dependent Claim
82 words
A system as defined in claim 7, further comprising: detecting means, connected to said coincidence means to detect the condition of at least two reply signals overlapping in time so that some of their time slots occur in exact time coincidence; and clear signal generating means, connected to said coincidence means to generate a clear signal in response to the occurrence of said overlapping condition, said clear signal being supplied to said code memory means to eliminate the data bits stored therein.
Claim 13
Dependent Claim
53 words
A system as defined in claim 10, further comprising: reset signal generating means, connected to said detecting means to generate a reset signal in response to the occurrence of said overlapping condition; said control circuits being repeatedly reset in response to said reset signal until they are set by their associated coincidence signals.
Claim 14
Dependent Claim
228 words
A decoder system useful in a radar beacon system for discussing between first and second reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: a delay line for converting said reply signals from serial to parallel form, said delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay line; an AND gate, connected to said delay line to produce a coincidence signal in response to each pair of said first and second framing pulses; a plurality of NAND gates, each connected to one of said delay line output taps to read out said data pulse from said delay line in response to said coincidence signal; and a register having a plurality of data bins, said register including comparator means for comparing the width of Each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.
Claim 15
Dependent Claim
228 words
A decoder system useful in a radar beacon system for discussing between first and second reply signals occurring in near time coincidence, each reply signal comprised of first and second framing pulses spaced in time by a fixed interval, and additionally including a plurality of data pulses, each able to occur during a corresponding time slot of a sequence of such time slots defined between said first and second framing pulses, comprising: a delay line for converting said reply signals from serial to parallel form, said delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving said data pulses from said delay line; an AND gate, connected to said delay line to produce a coincidence signal in response to each pair of said first and second framing pulses; a plurality of NAND gates, each connected to one of said delay line output taps to read out said data pulse from said delay line in response to said coincidence signal; and a register having a plurality of data bins, said register including comparator means for comparing the width of Each data pulse with that of its associated coincidence signal to accept or reject said data pulse dependent upon whether or not it has a width equal to that of said coincidence signal.
Claim 16
Dependent Claim
190 words
A system as defined in claim 12, in which each of said register data bins comprises: a main flip-flop, connected to the output of its associated NAND gate to set said main flip-flop upon receipt of each data pulse; a first NAND gate, connected to the outputs of said associated NAND gate and of said AND gate to enable said first NAND gate when said data pulse does not have a width equal to that of said coincidence signal; an auxiliary flip-flop, connected to the output of said first NAND gate to set said auxiliary flip-flop when said first NAND gate is enabled; a NOT gate, connected to the output of said AND gate to invert said coincidence signal; and a second NAND gate, connected to the outputs of said auxiliary flip-flop and of said NOT gate to enable said second NAND gate when said auxiliary flip-flop is in its set state and the trailing edge of said coincidence signal is detected, the output of said second NAND gate being connected to said main and auxiliary flip-flops to reset the same in response to said second NAND gate being enabled.
Claim 17
Dependent Claim
133 words
A system as defined in claim 12, further comprising: first and second control circuits, each associated with one of said first and second reply signals, each of said control circuits being responsive to only its associated coincidence signal for producing a transfer signal; first and second groups of AND gates, each of said AND gates in each group being connected to one of said register data bins and connected together to its associated control circuit to read out the data bit stored in said data bin in response to said transfer signal; and first and second code registers, each comprising a plurality of data bins, each of said code register data bins being connected to its associated AND gate to receive the data bit from said register in response to said transfer signal.
Claim 18
Dependent Claim
83 words
A system as defined in claim 14, in which said first and second control circuits are responsive to their associated coincidence signals to produce another transfer signals; first and second groups of another AND gates, each of said another AND gates in each group being connected to one of said data bins of its associated code register and connected together to its associated control circuit to read out the data stored in its associated code register in response to said another transfer signal.
Claim 19
Dependent Claim
22 words
A system as defined in claim 15, in which said another transfer signal is utilized as a radar echo to determine range.
Claim 20
Dependent Claim
171 words
A system as defined in claim 14, in which each of said first and second control circuits produces first and second gate signals in response to its associated coincidence signal, said first and second gate signals having a duration equal to the fixed time interval between said first and second framing pulses; a first AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal to said first control circuit only when said second gate signal from said first control circuit is present; a second AND gate, connected to said AND gate and said first control circuit to permit passage of said coincidence signal through said second AND gate only when said first gate signal from said first control circuit is present; and a third AND gate, connected to said second AND gate and said second control circuit to permit passage of said coincidence signal to said second control circuit only when said second gate signal from said second control circuit is present.
Claim 21
Dependent Claim
108 words
A system as defined in claim 17, further comprising: a fourth AND gate, connected to said first and second control circuits and also to said first group of AND gates to permit passage of said transfer signal from said first control cIrcuit to said AND gates only when said transfer signal from said second control circuit is absent; and a fifth AND gate, connected to said first and second control circuits and also to said second group of AND gates to permit passage of said transfer signal from said second control circuit to said AND gates only when said transfer signal from said first control circuit is absent.
Claim 22
Dependent Claim
186 words
A system as defined in claim 17, further comprising: another delay line, connected to the output of said AND gate to receive said coincidence signals, said another delay line having a time delay equal to the fixed interval between said first and second framing pulses and including a plurality of output taps for deriving a sequence of said coincidence signals which occur when said first and second reply signals overlap in time so that some of their time slots occur in exact time coincidence; an OR gate, connected to the output taps of said another delay line to enable said OR gate when said coincidence signal appears at any of said output taps; a sixth AND gate, connected to the input of said another delay line and also to the output of said OR gate to enable said sixth AND gate when said overlapping condition of the first and second reply signals is present; and means for generating a clear signal in response to said sixth AND gate being enabled, said clear signal being supplied to said first and second code registers to clear the same.
Claim 23
Dependent Claim
153 words
A system as defined in claim 19, further comprising: means for generating a reset pulse each time said sixth AND gate is enabled; said reset pulse being supplied to said second control circuit to reset the same; a seventh AND gate, connected to the outputs of said second AND gate, said reset pulse generating means and said second control circuit to enable said seventh AND gate in response to each of said coincidence signals except for the first and second occurring ones; and a second OR gate, connected to the outputs of said third AND gate and of said seventh AND gate to couple said coincidence signals to said second control circuit when said second OR gate is enabled; whereby said second control circuit is repeatedly reset in response to said reset pulses until it is set by the particular coincidence signal which results from the framing pulses of said second reply signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |