US3866176A
Expired / Lapsed
US
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Address selection circuit for storage arrays
Assignee: International Business Machines Corp
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Filing: 1974-01-31
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Granted: 1975-02-11
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Expires: 1994-01-31
Abstract
Abstract For each binary position of the coded addresses the selection device shows a phase splitter whose two outputs are connected to associated inputs of decoders. In order to increase the noise resistance jointly clocked AND gates are inserted at the inputs and outputs of the phase splitters, and at the outputs of the decoders. An automatic optimum determination of the conditioning time of the AND gates at the outputs of phase splitters is achieved by a delayed clock pulse DCS1 derived from a clock pulse T of AND gates at the input of the phase splitters. For that purpose, clock pulse T is derived at the output of the AND gates at the input of phase splitters and, via a simulated phase splitter circuit integrated on the chip, is applied as clock pulse DCS1 to the clock inputs of the AND gates at the output of the functional phase splitters. The determination of the conditioning time of AND gates at the output of the decoder is performed accordingly at the output of decoder. In that process, a clock signal is derived from the output of AND gates at the output of phase splitters, and applied as a delayed clock signal DCS2 via a simulation of one of decoders to the clock inputs of the AND gates at the output of the decoders.
Inventors
- 👤 Utz G Baitinger
- 👤 Werner Otto Haug
- 👤 Manfred Illi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:58
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/418; G11C11/414; G11C11/415; G11C5/00; G11C8/00; G11C8/18; H; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
147 words
A logic circuit for providing a delayed logical output signal on an output terminal, comprising: a first logic gating means for performing a predetermined logic function and for providing an inherently delayed output signal, said first logic gating means being responsive to at least one input signal; output gating means responsive to said first logic gating means for providing a logical signal to said output terminal corresponding to said predetermined logic function, said output gating means also being responsive to an output gating clock pulse; and clock pulse generating means for generating said output gating clock pulse after said first logic function has been performed, said clock pulse generating means comprising a second logic gating means for simulating the inherent time delay of said first logic gating means and for always providing a true logical output signal in response to at least one of said input signals.
Claim 2
Dependent Claim
147 words
A logic circuit for providing a delayed logical output signal on an output terminal, comprising: a first logic gating means for performing a predetermined logic function and for providing an inherently delayed output signal, said first logic gating means being responsive to at least one input signal; output gating means responsive to said first logic gating means for providing a logical signal to said output terminal corresponding to said predetermined logic function, said output gating means also being responsive to an output gating clock pulse; and clock pulse generating means for generating said output gating clock pulse after said first logic function has been performed, said clock pulse generating means comprising a second logic gating means for simulating the inherent time delay of said first logic gating means and for always providing a true logical output signal in response to at least one of said input signals.
Claim 3
Dependent Claim
30 words
The logic circuit of claim 1 wherein said second logic gating means includes logic gates for performing at least the same predetermined logic function as said first logic gating means.
Claim 4
Dependent Claim
46 words
The logic circuit of claim 2 further providing a plurality of first gating means responsive to a plurality of input signals, each of said first gating means providing the same predetermined logic function and having an associated output gating means responsive to said output gating pulse.
Claim 5
Dependent Claim
44 words
The logic circuit of claim 3 wherein said first logic gating means comprises a true-complement generator for performing at least a NAND logic function and said second logic gating means simulates the delay of said first logic gating means by performing a NAND function.
Claim 6
Dependent Claim
79 words
The logic circuit of claim 1 wherein said first logic gating means comprises a plurality of decoder circuits responsIve to the selected outputs of a plurality of true-complement generators, there being one true-complement generator for each binary position of a coded memory address, and further wherein said output gating means comprises a plurality of jointly clocked AND gates and said clock pulse generator comprises a simulated decoder circuit responsive to the two outputs of one of said true-complement generators.
Claim 7
Dependent Claim
29 words
The logic circuit of claim 5 wherein said simulated decoder circuit includes the same discrete devices as provided in the decoder circuit having the greatest inherently delayed output signal.
Claim 8
Dependent Claim
19 words
The logic circuit of claim 6 wherein all of said logic gates are integrated on the same semiconductor chip.
Claim 9
Dependent Claim
149 words
An address selection device for a monolithically integrated storage array having a true-complement generator for each binary position of a coded address word, wherein the outputs of said true-complement generators are connected to associated inputs of a plurality of decoder circuits and at the inputs and outputs of each true-complement generator, and at the output of each of said decoders, there is provided a plurality of jointly clocked AND gates for increasing noise resistance, the improvement comprising clock pulse source means for gating the AND gates at the input and output of each of said true-complement generators; decoder simulation means responsive to the outputs of the AND gates at the output of one of said true-complement generators for generating a delayed clock signal corresponding to the circuit delay of said decoders; and means connecting said clock signal to the AND gates at the output of each of said decoders.
Claim 10
Dependent Claim
149 words
An address selection device for a monolithically integrated storage array having a true-complement generator for each binary position of a coded address word, wherein the outputs of said true-complement generators are connected to associated inputs of a plurality of decoder circuits and at the inputs and outputs of each true-complement generator, and at the output of each of said decoders, there is provided a plurality of jointly clocked AND gates for increasing noise resistance, the improvement comprising clock pulse source means for gating the AND gates at the input and output of each of said true-complement generators; decoder simulation means responsive to the outputs of the AND gates at the output of one of said true-complement generators for generating a delayed clock signal corresponding to the circuit delay of said decoders; and means connecting said clock signal to the AND gates at the output of each of said decoders.
Claim 11
Dependent Claim
84 words
The address selection device of claim 8 wherein each true-complement generator has an input for one of the binary positions of an encoded low order address bit and an input for a higher order address bit and further wherein there is provided an AND gate responsive to said clock pulse source means and said higher order address, and means for applying the output of said last said AND gate to the clock inputs of the AND gates at the output of said true-complement generators.
Claim 12
Dependent Claim
47 words
The address selection device of claim 9 wherein the output of the AND gate responsive to said clock pulse source means and said higher order address is applied to the clock inputs of the AND gates of said true-complement generators through a simulation of a true-complement generator.
Claim 13
Dependent Claim
36 words
The address selection device of claim 10 wherein each of said true-complement generators comprise an AND and a NAND gate and said simulation of a true-complement generator comprises a NAND gate followed by an inverter gate.
Claim 14
Dependent Claim
34 words
The address selection device of claim 10 wherein each true-complement generator comprises an OR and a NOR gate and said simulation of a true-complement generator comprises a NOR gate followed by an inverter gate.
Claim 15
Dependent Claim
28 words
The address selection device of claim 8 wherein each decoder comprises a NOR gate and said decoder simulation means comprises a NOR gate followed by an inverter gate.
Claim 16
Dependent Claim
27 words
The address selection device of claim 8 wherein each decoder comprises an AND gate and said decoder simulator comprises an AND gate followed by an inverter gate.
Claim 17
Dependent Claim
16 words
The address selection device of claim 13 wherein said inverter comprises a fast switching bootstrap circuit.
References Cited (Backward Citations)
US3816725A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-10 | 1978-08-12 | 1979-02-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-10 | 1982-08-12 | 1983-02-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-10 | 1986-08-12 | 1987-02-11 | $7700.00 | Window Closed / Lapsed |