Gray-level angle-gated electro-optical seeker

Claim 2

In an electro-optical tracking system, the combination comprising: a. an imaging tube, b. a lens for focusing an image of the scene containing the target of interest on the face plate of said imaging tube, c. scan generation circuit means including a vertical trigger circuit, a horizontal voltage sweep generator and a vertical voltage sweep generator coupled to said imaging tube for electronically scanning the image focused on the face plate of said imaging tube, d. gray level tracking circuit means including gray level memory circuit means and first gated diodes coupling said imaging tube to said gray level memory circuit means for passing signals to said gray level memory circuit only when there is a change in the gray level signal from said imaging tube, and producing an output signal that is proportional to the gray level of the target being tracked, e. a gray level discriminating means coupled to said imaging tube and to said gray level tracking circuit means for producing an output signal when the signal received from the imaging tube is the same as the signal received from said gray level tracking circuit means, f. angle tracking circuit means coupled to said scan generation circuit means and to said gray level discriminating means for passing horizontal and vertical scan voltages in response to the signal from said gray level discriminator that represent the horizontal and vertical coordinates of objects having the same gray level as the target of interest and for then selectively passing only those voltages that represent approximately the same coordinates as the coordinates of the target of interest.

Claim 3

The system of claim 1 wherein said gray level discriminating means comprises: a. a gray level acceptance gate having an input and an output, b. a first comparator having a first input coupled to said imaging tube, a second input coupled to said gray level memory circuit and an output coupled to the input of said gray level acceptance gate for generating a blocking signal to said gray level acceptance gate when the signal received from said imaging tube is different from the signal received from said gray level memory circuit.

Claim 4

a second summing circuit having a first input coupled to the output of said second gated diode, a second input and an output,

Claim 5

a second summing circuit having a first input coupled to the output of said second gated diode, a second input and an output,

Claim 6

a first summing circuit having a first input coupled to the output of said first gated diode, a second input and an output,

Claim 7

a first summing circuit having a first input coupled to the output of said first gated diode, a second input and an output,

Claim 8

circuit means coupling the output of said staircase generator to the second input of said second summing circuit,

Claim 9

circuit means coupling the output of said staircase generator to the second input of said second summing circuit,

Claim 10

circuit means coupling the output of said integrator to the second input of said first summing circuit,

Claim 11

circuit means coupling the output of said integrator to the second input of said first summing circuit,

Claim 12

second gated diodes having a first input coupled to the output of said summing circuit, a second input and an output,

Claim 13

second gated diodes having a first input coupled to the output of said summing circuit, a second input and an output,

Claim 14

The system of claim 2 wherein said angle tracking circuit means comprises: a. first gating circuit means coupled to said gray level discriminator and to said horizontal voltage sweep generator for gating the horizontal sweep voltage in response to the gating signal from said gray level discriminator, b. a horizontal coordinate memory circuit having an output voltage that represents the horizontal coordinate of the target being tracked, c. A second comparator circuit coupled to said first gating circuit means and to said horizontal coordinate memory circuit means for generating an output signal when the two signals received by said second comparator are substantially the same, d. an angle gate generator coupled to said second comparator circuit means for generating an output gating signal in response to the output signal from said second comparator circuit, e. second gating circuit means coupled to said first gating circuit means, said angle gate generator and said horizontal coordinate memory circuit for gating the output voltage from said first gating circuit means to said horizontal coordinate memory circuit when a gating signal is received from said angle gate generator, f. third gating circuit means coupled to said vertical sweep generator and to said gray level discriminator for gating the vertical sweep voltage in response to the gating signal from said gray level discriminator, g. a vertical coordinate memory circuit having an output voltage that represents the vertical coordinate of the target being tracked, h. a third comparator circuit coupled to said vertical coordinate memory circuit and to said third gating circuit means for generating an output signal when the two signals received by said third comparator are substantially the same, i. said angle gate generator being coupled to said third comparator circuit for generating an output gating signal in response to the output signal from said third comparator circuit, j. fourth gating circuit means coupled to said third gating circuit means, said vertical coordinate memory circuit means and said angle gate generator for gating the output of said third gating circuit means to said vertical coordinate memory circuit when a gating signal is received from said angle gate generator.

Claim 15

a second sensitivity control circuit having an input coupled to the output of said staircase generator and an output,

Claim 16

a second sensitivity control circuit having an input coupled to the output of said staircase generator and an output,

Claim 17

second gated diodes having a first input coupled to the output of said second summing circuit, a second input and an output,

Claim 18

second gated diodes having a first input coupled to the output of said second summing circuit, a second input and an output,

Claim 19

a first sensitivity control circuit for controlling the amount of deviation a signal may have from the remembered horizontal coordinate and having a first input coupled to the output of saId integrator circuit, a second input and an output,

Claim 20

a first sensitivity control circuit for controlling the amount of deviation a signal may have from the remembered horizontal coordinate and having a first input coupled to the output of saId integrator circuit, a second input and an output,

Claim 21

The system of claim 2 wherein said angle tracking circuit means comprises: a. a horizontal channel for generating an output signal that represents the horizontal coordinate of the target of interest and having:

Claim 22

a second comparator circuit having a first input coupled to the output of said first sensitivity control circuit, a second input coupled to the output of said first gated diode, a third input coupled to the output of said horizontal coordinate memory circuit, and an output for producing an output signal when the signal received from said first gated diode is different from that of the signal received from the output of horizontal coordinate memory circuit,

Claim 23

a second comparator circuit having a first input coupled to the output of said first sensitivity control circuit, a second input coupled to the output of said first gated diode, a third input coupled to the output of said horizontal coordinate memory circuit, and an output for producing an output signal when the signal received from said first gated diode is different from that of the signal received from the output of horizontal coordinate memory circuit,

Claim 24

a third comparator circuit having a first input coupled to the output of said second sensitivity control circuit, a second input coupled to the output of said second gated diode, a third input coupled to the output of said vertical coordinate memory circuit and an output for producing an output signal when the signal received from said second gated diode is different from that of the signal received from the output of horizontal coordinate memory circuit,

Claim 25

a third comparator circuit having a first input coupled to the output of said second sensitivity control circuit, a second input coupled to the output of said second gated diode, a third input coupled to the output of said vertical coordinate memory circuit and an output for producing an output signal when the signal received from said second gated diode is different from that of the signal received from the output of horizontal coordinate memory circuit,

Claim 26

a horizontal memory circuit having an input coupled to the output of said second gated diodes and an output, b. a vertical channel for generating an output signal that represents the vertical coordinate of the target of interest and having:

Claim 27

a horizontal memory circuit having an input coupled to the output of said second gated diodes and an output, b. a vertical channel for generating an output signal that represents the vertical coordinate of the target of interest and having:

Claim 28

a vertical memory circuit having an input coupled to the output of said second gated diodes and an output, c. a horizontal coordinate voltage selecting circuit having:

Claim 29

a vertical memory circuit having an input coupled to the output of said second gated diodes and an output, c. a horizontal coordinate voltage selecting circuit having:

Claim 30

a horizontal acceptance gate having an input coupled to the output of said second comparator and an output for producing an output signal except when a signal is received from said second comparator circuit, d. a vertical coordinate voltage selecting circuit having:

Claim 31

a horizontal acceptance gate having an input coupled to the output of said second comparator and an output for producing an output signal except when a signal is received from said second comparator circuit, d. a vertical coordinate voltage selecting circuit having:

Claim 32

a vertical acceptance gate having an input coupled to the output of said second comparator circuit and having an output for producing an output signal except when a signal is received from said second comparator circuit, e. an angle gate generator for controlling the operation of said first, second and third gated diodes, said staircase generator, and said first sensitivity control circuit and having a first input coupled to the output of said horizontal acceptance gate circuit, a second input coupled to the output of said vertical acceptance gate circuit and an output coupled to second inputs of said first, second, and third gated diodes, said first sensitivity control circuit, and said staircase generator, respectively.

Claim 33

a vertical acceptance gate having an input coupled to the output of said second comparator circuit and having an output for producing an output signal except when a signal is received from said second comparator circuit, e. an angle gate generator for controlling the operation of said first, second and third gated diodes, said staircase generator, and said first sensitivity control circuit and having a first input coupled to the output of said horizontal acceptance gate circuit, a second input coupled to the output of said vertical acceptance gate circuit and an output coupled to second inputs of said first, second, and third gated diodes, said first sensitivity control circuit, and said staircase generator, respectively.