Detection of digital data using integration techniques

Claim 2

A data detector, including in combination: means for receiving an amplitude-limited signal having first and second signal states; timing means responsive to said limited signal to generate a clock signal indicative of pairs of first and second successive sample times for said limited signal; first, second, third, and fourth integration means each supplying an integrated signal, said first and second means being responsive to said clock signal respectively during said first and second sample times to integrate said limited signal only when said limited signal is in said first signal state, said third and fourth integration means being responsive to said clock signal to integrate said limited signal only when said limited signal is in said second signal state, respectively during said first and second sample times, each of said integration means being respectively nonresponsive to said limited signal at all other times; reference signal recovery means in each said integration means for altering the integrated signal therein when the respective integration means are nonresponsive to said limited signal for altering each integrated signal toward a reference signal value; separate means for combining said integrated signals from said first and second integration means and for combining said integrated signals from said third and fourth integrator means; and output means responsive to said combined signals for indicating data in accordance with the signal relationships Therebetween.

Claim 3

The subject matter of claim 1 wherein said recovery means alters the integration means signal state at a rate such that a substantial portion of one of said sample times is required for said alteration.

Claim 4

The subject matter of claim 1 wherein said clock signal has first and second signal states respectively indicating said first and second successive sample times; integrator clocking means electrically interposed between said timing means and each integration means for selectively activating same in accordance with the signal states of said clock signal, a first integrator clocking means being responsive to said clock signal to actuate said first and third integration means to receive said limited signal and to respectively integrate said first and second signal states thereof and simultaneously actuating said second and fourth integration means to alter the integrated signals therein toward a reference state during substantially all of said first sample times; and said integrator clocking means being further responsive to said clocking signal being in said second signal state to cause said second and fourth integration means to be responsive to said limited signal and simultaneously causing said first and third integration means to alter the integrated signal toward a reference signal state during substantially all of said second sample time.

Claim 5

The subject matter of claim 3 wherein said integrator clocking means has a pair of constant current sources for each integration means, said constant current sources supplying a constant drive current to each of the respective integration means for providing linear ramp integration based upon duration of said first and second signal states within said limited signal during the respective sampling times.

Claim 6

The subject matter set forth in claim 1 wherein said output means includes an amplitude voltage comparator responsive at predetermined times within said sample times to same combined signals for providing a binary output signal for indicating which of the two combined signals has the larger amplitude.

Claim 7

The subject matter set forth in claim 5 wherein said comparator means includes a bistable latch having first and second inputs for respectively switching the latch between first and second stable signal states; strobe means connected to said latch for selectively biasing said latch to an inactive circuit condition and further biasing said latch to an active circuit condition for a short period of time at the beginning of each of said sample times such that the combined signals bias the first and second inputs respectively for causing said latch to rapidly switch to one of said first or second signal states during said short period.

Claim 8

The subject matter set forth in claim 6 further including a constant current source in said output means, a pair of emitter followers electrically interposed between said combining means and inputs to said latch and being supplied emitter current by said output means constant current means such that sensitivity of the comparator means to the differences between amplitudes of said combined signals is enhanced.

Claim 9

The data detector set forth in claim 1 further including first and second integrated signal storage means respectively differentially coupled between said first and third and said second and fourth integration means for alternately storing integration signals therefrom, respectively.

Claim 10

The data detector set forth in claim 8 including two pairs of reversably switched current sources, current sources in said pairs being switchable between said differential connection of each said storage means, respectively, and one of said current sources in each pair being time shared by two of said integration means, respectively, as said reference signal-state recovery means.

Claim 11

The data detector set forth in claim 8 further including a constant current source; and wherein said timing means includes a pair of alternatEly actuated solid-state switching means respectively electrically interposed between said first and third, said second and fourth integration means, and said constant current source.

Claim 12

The data detector set forth in claim 10 wherein each integration means includes a first semiconductive switch means having a data signal receiving connection for respectively receiving said limited signal, and a second emitter-follower configured semiconduction switch means having a control connection to the respective first switch means and an emitter portion respectively connected to said storage means for establishing said differential coupling.

Claim 13

The data detector set forth in claim 1 wherein said integration means each includes transistor switch means jointly responsive to said clock and to said data for assuming current conductive and nonconductive states in accordance with the relationship between the clock and said data, and having an output terminal reflecting said conductive state; first and second capacitor means connected across output terminals of said integration means respectively actuated by the same clock phase, said first and third and said second and fourth integration means respectively; current source means for exchanging current of a first amplitude for providing an integration signal; second current source means comprising said reference state signal recovery means for exchanging electrical current for recovering said capacitors from an integrated charge; reversing switch means in said reference state recovery means and said integration means selectively and alternately switching said first and second current source means between the output terminals of said first and third and said second and fourth integration means such that capacitor means alternately exchange integration currents respectively with said first and second or said third and fourth integration means and with said signal-state recovery means; high-input impedance amplifier means connected to each of said output terminals; and said separate means receiving signals from said amplifier means.

Claim 14

Predetection integration for use with amplitude limited signals, a first-limited signal being supplied along a first line and a second limited signal being supplied along a second line; timing means responsive to one of said limited signals for generating a clocking signal having first and second signal states of respective durations substantially equal to predetermined durations of corresponding first and second signal states of said one limited signal; first integration means jointly responsive to said first limited signal being in a first signal state and to said clock signal being in a first signal state to integrate time duration of said limited signal being in said first signal state and being further responsive to said clock signal being in a second signal state to alter the integrated signal toward a reference state at a rate slightly greater than said rate of integration; second integration means jointly responsive to said first limited signal being in said first signal state and to said clock signal being in said second signal state to integrate the duration of said limited signal being in said first signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference value at a rate sightly greater than the rate of integration; third integration means jointly responsive to said second limited signal being in a second signal state and to said clock signal being in said first signal state to integrate the duration of said second limited signal being in said second signal state and being further responsive to said clock signal being in said signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; fourth integration means jointly responsive to said second limited signal being in said seCond signal state and to said clock signal being in said second signal state to integrate the duration of said limited signal being in said second signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; and signal combining means respectively combining the integrated signals from said first and second integration means for supplying a first combined signal indicating duration of the first signal state in said first limited signal and further combining integrated signals from said third and fourth integrator means for supplying a second combined signal indicating the duration of said second limited signal being in said second signal state.

Claim 15

Predetection integration for use with amplitude limited signals, a first-limited signal being supplied along a first line and a second limited signal being supplied along a second line; timing means responsive to one of said limited signals for generating a clocking signal having first and second signal states of respective durations substantially equal to predetermined durations of corresponding first and second signal states of said one limited signal; first integration means jointly responsive to said first limited signal being in a first signal state and to said clock signal being in a first signal state to integrate time duration of said limited signal being in said first signal state and being further responsive to said clock signal being in a second signal state to alter the integrated signal toward a reference state at a rate slightly greater than said rate of integration; second integration means jointly responsive to said first limited signal being in said first signal state and to said clock signal being in said second signal state to integrate the duration of said limited signal being in said first signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference value at a rate sightly greater than the rate of integration; third integration means jointly responsive to said second limited signal being in a second signal state and to said clock signal being in said first signal state to integrate the duration of said second limited signal being in said second signal state and being further responsive to said clock signal being in said signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; fourth integration means jointly responsive to said second limited signal being in said seCond signal state and to said clock signal being in said second signal state to integrate the duration of said limited signal being in said second signal state and being further responsive to said clock signal being in said first signal state to alter the integrated signal toward a reference state at a rate slightly greater than the rate of integration; and signal combining means respectively combining the integrated signals from said first and second integration means for supplying a first combined signal indicating duration of the first signal state in said first limited signal and further combining integrated signals from said third and fourth integrator means for supplying a second combined signal indicating the duration of said second limited signal being in said second signal state.

Claim 16

The subject matter set forth in claim 13 further including voltage comparison means including bistable means jointly responsive to said combined signals for setting the bistable means to a first signal state when the first combined signal has an amplitude greater than the second combined signal and to the second signal state in the reverse situation, a change in the stable states of bistable means indicating that said limited signals have changed signal states.

Claim 17

The subject matter set forth in claim 14 wherein each of said integration means includes a constant current source, a transistor device connected in grounded-base configuration having a collector electrode and an emitter electrode, said emitter electrode for receiving said limited signal for passing same whenever a constant current is received, an integrating capacitor in each of said integrators being connected to the collector of said grounded base transistor device; and recovery circuit means connected to said capacitor respectively in each of said integration means for causing current transfer at a rate greater than that provided by said grounded base transistor device and in the direction causing a recovery of said capacitor charge toward a reference value.

Claim 18

The subject matter set forth in claim 15 wherein each integration means includes an input-gate transistor having a base connection receiving said clock signals, respectively, and having a collector electrically connected to each base electrode of said grounded-base configuration transistor devices for clamping same to an off condition in response to said clock signal respectively and when current nonconductive preventing a constant-current flow to said base electrode.

Claim 19

The subject matter set forth in claim 14 wherein said voltage-comparison means has first and second transistor means cross-coupled to form said bistable means, said first and second transistor means having emitter electrodes connected together and with collector electrodes forming output connections; a strobe circuit for said voltage-comparison means comprising grounded-base transistor means having a pair of current passing electrodes one of which is connected to said commonly connected emitter electrodes and the other of which is for receiving a strobe signal; strobe means responsive to said timing means for selectively supplying said strobe signal for actuating said strobe circuit to a given current-conductive state; voltage-actuating means connected to said common emitter means and operative when said strobe circuit is in said given current-conductive state to effect current flow through said first and second transistor means such that said latch is in an active state for being responsive to inputs supplied from said signal combining means, and being further operative when said strobe circuit transistor is not in said given current-conductive state bias said first and second transistor means to be current nonconductive.

Claim 20

The subject matter of claim 17 further including a pair of output transistor means having collector electrodes commonly connected together and a base electrode respectively connected to the collector electrodes of said first anD second transistor means and emitter electrodes being output connections, unidirectional current-conducting means connected between a reference potential and said commonly-connected collectors, and a pair of gating means connected to said output emitter connections and receiving signals from said timing means for selectively actuating said gating means at least during the period of time said strobe circuit is in said given current-conductive state.

Claim 21

The subject matter set forth in claim 18 further including a differential amplifier having two transistor means respectively receiving said first and second combined signals and having emitter electrodes commonly connected together; a constant-current source causing a constant current flow through said differential amplifier, said differential amplifier being operative to provide current division in accordance with the amplitude differences of said combined signals; and electrical connections between said differential amplifier and said first and second transistors.

Claim 22

The predetection integration set forth in claim 13 further including first and second integration signal storage means respectively extending between said first and third and said second and fourth integration means, and current switching means alternately causing said capacitors to exchange integrating current or said slightly greater rate of current in alternately successive cycles.

Claim 25

The method of claim 21 wherein said input digital signal may have more than one state change in each time period, generating a reference digital signal having predetermined cyclic signal state changes, logically combining said input and reference digital signal to produce a third digital signal having fewer state changes per time period than said input digital signal, and then integrating said third digital signal in place of integrating said input digital signal.

Claim 26

The method of claim 21 wherein the combining step includes forming the analog-OR signal of the two independently integrated signals for each signal state and differentially comparing said analog-OR signals and supplying said output signal in accordance with one of said analog-OR signals having a predetermined signal relationship to others of said analog-OR sums.

Claim 27

The method of claim 23 wherein based upon said differential comparison an output signal is supplied indicating that said one analog-OR signal has the greatest signal amplitude of a given polarity.

Claim 28

The method of claim 23 wherein based upon said differential comparison an output signal is supplied indicating whether or not two analog-OR signals have a given amplitude difference therebetween.

Claim 29

A digital signal detector including the combination: first and second integrators, each integrator having + and -integration circuits; data means supplying a first digital signal to said first integrator and a second digital signal to said second integrator; clock means supplying + and - digital clock signals to said + and - integration circuits respectively for alternately activating said integration circuits to integrate said data signals; and means receiving said integrated signals and combining same in a predetermined manner and responsive to one of said clock signals to supply an output signal indicative of the signal relationships of said integrated signals.

Claim 30

A digital signal detector including the combination: first and second integrators, each integrator having + and -integration circuits; data means supplying a first digital signal to said first integrator and a second digital signal to said second integrator; clock means supplying + and - digital clock signals to said + and - integration circuits respectively for alternately activating said integration circuits to integrate said data signals; and means receiving said integrated signals and combining same in a predetermined manner and responsive to one of said clock signals to supply an output signal indicative of the signal relationships of said integrated signals.

Claim 31

The detector set forth in claim 26 wherein said integration circuits responsive to said + clock signal to integrate a digital signal being responsive only when said + clock signal is in a first signal state and when said clock signal is in a signal state other than said first signal state said + clock integration circuits altering its said integrated signals at a given rate toward a reference potential, said integration circuits responsive to said - clock signal to integrate a digital signal being responsive only when said -clock signal is in a first signal state and when said - clock signal is in a signal state other than said first signal state, said - clock integration circuits altering its said integrated signals at a given rate toward a reference potential, and said given rate being only slightly greater than the rate of integrating said digital signals.

Claim 32

The detector set forth in claim 27 wherein each integration circuit is operative to maintain an integrated signal whenever the respective input digital signal is not in a signal state to be integrated during the period of time such integration circuit is being activated to integrate such respective input digital signal.

Claim 33

The detector set forth in claim 28 wherein said clock means is responsive to one of said input digital signals to generate digital clock signals having a given periodicity and being symmetrical, said periodicity being such that integration of an input digital signal during one clock signal state reaching a maximum amplitude and said given rate altering such integrated maximum signal in about 75 percent of such integration time.

Claim 34

The detector set forth in claim 26 wherein said receiving means includes a differential comparison circuit, two summing means each combining two of said integrated signals and supplying such combined signals to the differential comparison circuit, said combining means activating said differential comparison circuit to supply an output signal each time said clock signals change signal states, and constant-current means supplying separate constant currents to said differential comparison circuit at an input receiving said combined signals, at an output for said output signal.

Claim 35

The digital signal detector set forth in claim 26 further including capacitor means extending between said + and said -integration circuits in said integrators, respectively, and receiving integration signals therefrom on a time-shared basis; and current exchanging means connected to said capacitors and said integration circuits and including switching means responsive to said clock means for alternately and successively connecting an integrating signal and a recovery signal for said integration circuit with respect to said capacitor means.

Claim 36

The data detector set forth in claim 31 wherein said clocking means comprises first and second semiconductor switching means alternately in conductive and nonconductive signal states; and said + integration circuits being connected to and responsive to the signal state of one of said semiconductive switch means and said - integration circuits being connected to and responsive to the signal state of the other of said semiconductive switch means.

Claim 37

A signal processing circuit for receiving first and second input signals to be compared; clock means responsive to one of said signals to establish successive time period clock signals having a predetermined relationship to said input signals; a first integrator having two first integration means and responsive to said first input Signal and to said clock signals to integrate said first signal alternately in said first integration means, respectively, and to supply a first integrated output signal based upon the integrated signals in said first integration means; a second integrator having two second integration means responsive to said second input signal and to said clock signal to integrate said second input signal alternatively in said second integration means, respectively, and to supply a second integrated output signal based upon the integrated signals in said second integration means; and output means receiving said output integrated signals and combining same to supply a signal in accordance with said combination.

Claim 38

A signal processing circuit for receiving first and second input signals to be compared; clock means responsive to one of said signals to establish successive time period clock signals having a predetermined relationship to said input signals; a first integrator having two first integration means and responsive to said first input Signal and to said clock signals to integrate said first signal alternately in said first integration means, respectively, and to supply a first integrated output signal based upon the integrated signals in said first integration means; a second integrator having two second integration means responsive to said second input signal and to said clock signal to integrate said second input signal alternatively in said second integration means, respectively, and to supply a second integrated output signal based upon the integrated signals in said second integration means; and output means receiving said output integrated signals and combining same to supply a signal in accordance with said combination.

Claim 39

The signal processing circuit set forth in claim 33 further including first and second integrated signal storage means respectively extending between said first and second integration means respectively alternately actuated for integrating; and switching means alternately actuating said integration means for effecting integration and squelching in successive time periods from said first and second integrators.

Claim 40

Synchronous demodulation employing integration, including the following steps in combination: supplying a timing signal; supplying data signals to be synchronously demodulated with respect to said timing signal; combining said timing signal and said data signals to generate four distinct signal amplitudes including integrating said data signals with respect to said timing signals; and in timed relation to said timing signal, combining said distinct signal amplitudes into two signals and then amplitude comparing the two signals to generate an output signal timed by said timing signal and representing said data signal in a synchronous demodulated relation to said timing signal.

Claim 41

Synchronous demodulation employing integration, including the following steps in combination: supplying a timing signal; supplying data signals to be synchronously demodulated with respect to said timing signal; combining said timing signal and said data signals to generate four distinct signal amplitudes including integrating said data signals with respect to said timing signals; and in timed relation to said timing signal, combining said distinct signal amplitudes into two signals and then amplitude comparing the two signals to generate an output signal timed by said timing signal and representing said data signal in a synchronous demodulated relation to said timing signal.

Claim 42

A pair of integrating circuits for use in a synchronous demodulation scheme comprising: clocking control means; first and second electronic switches responsive to first and second input signals for assuming conductive and nonconductive states and each having a connection to said clocking circuit for being alternately actuated thereby; storage means extending between said first and second integrating circuits; first and second current sources; reversing switching means connected on opposite sides of said storage means and to said current sources, and responsive to said clock signal to alternately connect said current sources to opposite sides of said storage means in synchronous relationship to the received data signal whereby said storage means alternately exchanges integrating signals in accordance with the signal state of said switch and said clock and squelching signals in successive timed clock periods; and means receiving signals from the opposite sides of said capacitor for performing a function in accordance with the relative amplitudes thereof.

Claim 43

A pair of integrating circuits for use in a synchronous demodulation scheme comprising: clocking control means; first and second electronic switches responsive to first and second input signals for assuming conductive and nonconductive states and each having a connection to said clocking circuit for being alternately actuated thereby; storage means extending between said first and second integrating circuits; first and second current sources; reversing switching means connected on opposite sides of said storage means and to said current sources, and responsive to said clock signal to alternately connect said current sources to opposite sides of said storage means in synchronous relationship to the received data signal whereby said storage means alternately exchanges integrating signals in accordance with the signal state of said switch and said clock and squelching signals in successive timed clock periods; and means receiving signals from the opposite sides of said capacitor for performing a function in accordance with the relative amplitudes thereof.

Claim 44

The circuit set forth in claim 36 wherein each of said integration switch means includes a pair of NPN transistor means, the emitter of one of said transistor means being connected to said clock means; a resistor means extending between the collectors of said transistor means, and electrical connection between the collector of said one transistor means to a controlled portion of a second of said transistor means with the collector of said second transistor means being connected to a reference potential, and the emitter portion of said second transistor means being connected respectively to opposite end portions of said capacitor storage means, and said integrating current source being activated in timed relationship with said second transistor means being in a current nonconductive state in accordance with the data signal received by said integrating means and always being current conductive when said squelching current source is connected thereto; and means connected to supply data signals to said first one transistor means.

Claim 45

A synchRonous demodulation circuit employing integration techniques including first and second ones of integrators constructed as set forth in claim 37 including additional clocking means for a second one of said integrators and alternately actuated with respect to the first-mentioned clocking means; and analog-OR means receiving signals from alternately actuated ones of said integrators for establishing two signals in successive time periods alternately supplied by said alternately actuated integration means, and means in said receiving means for comparing signal amplitudes for establishing an output signal having a synchronous demodulated relationship to said clock signal based upon the receipt of said data signal whereby noise is eliminated from said data signal.

Claim 46

An electrical signal processing circuit, including in combination: means for differentially receiving a signal to be processed; a differentially operating time circuit for defining successive time periods of signal processing; first and second differentially connected switches each with first and second differential inputs and outputs differentially receiving said signal to be processed, and said switches being alternately actuated in said successive time periods between electrical current conductive and nonconductive states by said timing circuit and further responsive to said signal to be processed to alter one of said states; integration signal storage means extending between said outputs of said differentially connected switches, respectively; and means for detecting electrical signals in said storage means in timed relation to said time periods.

Claim 47

An electrical signal processing circuit, including in combination: means for differentially receiving a signal to be processed; a differentially operating time circuit for defining successive time periods of signal processing; first and second differentially connected switches each with first and second differential inputs and outputs differentially receiving said signal to be processed, and said switches being alternately actuated in said successive time periods between electrical current conductive and nonconductive states by said timing circuit and further responsive to said signal to be processed to alter one of said states; integration signal storage means extending between said outputs of said differentially connected switches, respectively; and means for detecting electrical signals in said storage means in timed relation to said time periods.

Claim 48

The electrical signal processing circuit of claim 39 further including in combination: two differential amplifier means having differential input portions respectively connected across said storage means and supplying output signals in accordance therewith; and analog-OR mixing means combining signals from said amplifier means in a predetermined manner and supplying mixed signals to said detecting means.

Claim 49

The electrical signal processing circuit of claim 39 further including in combination: integrating current source means and squelch current source means; and reversing switching means connecting said source means to said storage means in alternating reverse connections on opposite ends thereof in timed relation with said responsiveness to said signal to be processed of differentially connected switches such that said squelch current means is continuously acting on said storage means but in opposite electrical senses during successive periods of time in accordance with said timing circuit.

Claim 50

A data detector, including in combination: means for receiving a data signal having plural signal states to be detected; timing means repeatedly establishing first and second successive detection periods; first and second integration means respectively responsive to said data signal during said first and second detection periods to integrate a first signal state portion of said data signal and respectively during said second and first detection periods adjusting its integration state toward a reference integration state, and each supplying an integrated signal indicative of its respective integration states; and output means combining said integrated signals to a combined signal and responsive to said timing means and said combined signal to indicate data in accordance with said combined signal.

Claim 51

A data detector, including in combination: means for receiving a data signal having plural signal states to be detected; timing means repeatedly establishing first and second successive detection periods; first and second integration means respectively responsive to said data signal during said first and second detection periods to integrate a first signal state portion of said data signal and respectively during said second and first detection periods adjusting its integration state toward a reference integration state, and each supplying an integrated signal indicative of its respective integration states; and output means combining said integrated signals to a combined signal and responsive to said timing means and said combined signal to indicate data in accordance with said combined signal.

Claim 52

The data detector set forth in claim 42 further including means in said output means for detecting the amplitude of the integrated signal output from said integration means and supplying said combined signal in accordance with said detection for indicating value of the bit in each said detection period.

Claim 53

The apparatus of claim 43 further comprising means for generating said binary input signal from phase encoded data signals including in combination: said timing means Including a variable frequency clock for generating a clock signal slaved to said phase encloded data signal, each clock cycle of said clock signal representing one of said bit periods of said phase encoded data signal and said binary input signal and equal in duration to said detection period; and an exclusive-OR circuit receiving said clock signal and said phase encoded data signal to generate said data signal.

Claim 54

The apparatus of claim 43 further including in combination: said clock supplying complementary first and second clock signals; first AND gate means coupled between the output of said exclusive-OR means and said first integration means, said first AND gate means being enabled by said first clock signal so as to enable said first AND gate means during said first ones detection periods; and second AND gate means coupled between the output of said exclusive-OR means and said second integration means, said second AND gate means being coupled to and enabled by a second clock signal so as to enable said second AND gate means during said second detection periods.

Claim 55

The apparatus of claim 45 wherein said first integration means and said second integration means each comprise: integration circuit elements; and switch means responsive to the output of the respective AND gate means and said complementary clock signals, said switch means applying a signal for integration to the input of said integrating circuit elements during said first and second detection periods and supplying a signal to adjust said integration states in said circuit elements, respectively, in said second and first detection periods.

Claim 56

A circuit for integrating a binary input signal comprising a series of bit cells having fixed bit periods, said bit cells being spaced from one another by at least one bit period, said circuit comprising: an integrating means generating an output signal representing the integration of said input signal during said bit cells, means returning said output signal to a squelch level between said bit cells; clock means supplying a clock signal identifying said bit periods; and a switch means responsive to said input signal and said clock signal representing the spacing of said bit cells and supplying a signal for integration to said integration means during said bit periods of said bit cells and supplying a signal to squelch said integration means between said bit cells.

Claim 57

A circuit for integrating a binary input signal comprising a series of bit cells having fixed bit periods, said bit cells being spaced from one another by at least one bit period, said circuit comprising: an integrating means generating an output signal representing the integration of said input signal during said bit cells, means returning said output signal to a squelch level between said bit cells; clock means supplying a clock signal identifying said bit periods; and a switch means responsive to said input signal and said clock signal representing the spacing of said bit cells and supplying a signal for integration to said integration means during said bit periods of said bit cells and supplying a signal to squelch said integration means between said bit cells.

Claim 58

A pair of the circuits of claim 47 wherein the bit cells of one binary signal for one of said circuits are displaced in time with respect to the bit cells of another binary input signal for the other of said circuits.

Claim 61

The method of claim 49 further including the step of: dividing said bInary signal into complementary binary signals, the first of said complementary binary signals occurring during said alternate bit cells and the second of said signals occuring during said succeeding alternate bit cells, said first complementary binary signal and said second complementary binary signal being integrated by said first integrator and said second integrator, respectively.

Claim 62

Apparatus for integrating a binary input signal read from a magnetic tape comprising a series of bit cells including: a clock means synchronized with said bit cells of said binary signal; a means for dividing said input signal into a first binary signal comprising a first set of said bit cells representing both binary values and a second binary signal comprising a second set of said bit cells representing both binary values, the respective bit periods for bit cells in said first set lying between the respective bit periods for bit cells in said second set; a first integrating means having said first binary signal applied to the input thereof, said first integrating means integrating said first binary signal during said first set of bit cells irrespective of the binary values of said bit cells, said clock means being coupled to said first integrating means for controlling integration of said binary signal during said first set of bit cells in said series, said clock means also controlling squelching of said first integrating means so as to squelch said first integrating means during said second set of bit cells; a second integrating means having said second binary signal applied to the input thereof, said second integrating means integrating said second binary signal during said second set of bit cells irrespective of the binary values of said bit cells, said clock means being coupled to said second integrating means for controlling integration of said binary signal during said second set of bit cells in said series, said clock means also controlling squelching of said second integrating means so as to squelch said second integrating means after said second set of bit cells; and a means coupled to said first integrating means and said second integrating means for detecting the level of the integrated binary signals for each bit cell in said first set and said second set to determine the value of the bit in each bit cell.

Claim 63

Apparatus for integrating a binary input signal read from a magnetic tape comprising a series of bit cells including: a clock means synchronized with said bit cells of said binary signal; a means for dividing said input signal into a first binary signal comprising a first set of said bit cells representing both binary values and a second binary signal comprising a second set of said bit cells representing both binary values, the respective bit periods for bit cells in said first set lying between the respective bit periods for bit cells in said second set; a first integrating means having said first binary signal applied to the input thereof, said first integrating means integrating said first binary signal during said first set of bit cells irrespective of the binary values of said bit cells, said clock means being coupled to said first integrating means for controlling integration of said binary signal during said first set of bit cells in said series, said clock means also controlling squelching of said first integrating means so as to squelch said first integrating means during said second set of bit cells; a second integrating means having said second binary signal applied to the input thereof, said second integrating means integrating said second binary signal during said second set of bit cells irrespective of the binary values of said bit cells, said clock means being coupled to said second integrating means for controlling integration of said binary signal during said second set of bit cells in said series, said clock means also controlling squelching of said second integrating means so as to squelch said second integrating means after said second set of bit cells; and a means coupled to said first integrating means and said second integrating means for detecting the level of the integrated binary signals for each bit cell in said first set and said second set to determine the value of the bit in each bit cell.

Claim 64

The apparatus of claim 51 further comprising: a source of phase encoded data, said clock means including a variable frequency oscillator means coupled to the output of said source for generating a clock signal slaved to said phase encoded data, each clock cycle of said clock signal representing a bit period for a bit cell of said phase encoded data and said binary input signal; and an exclusive-OR means coupled to said source and said oscillator means for generating said binary input signal from said clock signal and said phase encoded data.

Claim 65

The apparatus of claim 52 wherein said clock means further includes a flip-flop means coupled to said oscillator means and set by said clock signal, said apparatus further comprising: a first AND gate means coupled between said exclusive-OR means and said first integrating means, said first AND gate being coupled to and enabled by a first output of said flip-flop means so as to enable said first AND gate means during said first set of bit cells; and a second AND gate means coupled between said exclusive-OR means and said second integrator means, said second AND gate means being coupled to and enabled by a second output of said flip-flop means so as to enable said second AND gate means during said second set of bit cells.

Claim 66

The apparatus of claim 53 wherein said first integrating means and said second integrating means each comprise: an integrating circuit element; and a switch means coupled to the output of the respective AND gate means, said flip-flop means, and said integrating circuit element, said switch means applying a signal for iNtegration to the input of said integrating circuit element during bit periods of said bit cells in one of said sets and applying a signal to squelch said integrating circuit element between the bit cells in said one set.

Claim 67

A signal processing circuit for a received signal representing data in successive bit periods by successive given signal-state change characteristics, the improvement including in combination: a clock responsive to said received signal to establish first and second alternating successive data detection period control signals; a first integrator jointly responsive to said first control signal and to said received signal to supply an output signal indicative of the relationship therebetween in each first detection period; a second integrator jointly responsive to said second control signal and to said received signal to supply an output signal indicative of the relationship therebetween in each second detection period; an output circuit receiving and combining said output signals to supply a single output signal indicative of the relationship of said control signals to said received signal during each detection period; and means in each said first and second integrators re-establishing a reference integration state respectively during said second and first detection periods.

Claim 68

A signal processing circuit for a received signal representing data in successive bit periods by successive given signal-state change characteristics, the improvement including in combination: a clock responsive to said received signal to establish first and second alternating successive data detection period control signals; a first integrator jointly responsive to said first control signal and to said received signal to supply an output signal indicative of the relationship therebetween in each first detection period; a second integrator jointly responsive to said second control signal and to said received signal to supply an output signal indicative of the relationship therebetween in each second detection period; an output circuit receiving and combining said output signals to supply a single output signal indicative of the relationship of said control signals to said received signal during each detection period; and means in each said first and second integrators re-establishing a reference integration state respectively during said second and first detection periods.