US3864549A
Expired / Lapsed
US
⏱️ 0.0 years remaining
N-position scanner having plural sequentially enabled decoders
Assignee: Vertex Industries Inc
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Filing: 1973-12-07
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Granted: 1975-02-04
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Expires: 1993-12-07
Abstract
Abstract An n-position scanner is disclosed which includes a two stage binary counter. The first stage of the binary counter is coupled to a plurality of 1-of-16 decoders for providing sequential scanning signals to each of the decoders. The second stage of the binary counter is coupled either directly or through logic networks to control inputs of each of the plurality of 1-of-16 decoders for enabling each of the plurality of decoders in a proper sequence. The 1-of-16 decoders may be used in combination to scan a card reader or any equivalent contact matrix or apparatus. The card reader or equivalent apparatus may include circuits for initiating and terminating scanning cycles.
Inventors
- 👤 Michael Joseph Yaccino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:48
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/01; G06K7/016
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
183 words
A multiple position scanning circuit comprising: first and second interconnected binary counters, each binary counter having a plurality of stages; counter stage output means coupled to each of said plurality of stages for providing output signals representative of the state of each said stage, a source of clock signals coupled to said binary counters for permitting said counters, a plurality of 1-of-n decoders coupled to said binary counters, each having a plurality of decoding inputs, a plurality of enabling inputs and a plurality of scanning outputs, first circuit means coupled between said counter stage output means of said first binary counter and said decoding inputs of each of said decoders for applying said signals representative of the state of each counter stage to said decoders; and, second circuit means coupled between at least one of said counter stage output means of said second binary counter and said enabling inputs of each of said decoders for sequentially enabling said plurality of decoders, whereby said scanning outputs of said plurality of decoders are sequentially scanned as said clock signals are applied to said binary counters.
Claim 2
Dependent Claim
183 words
A multiple position scanning circuit comprising: first and second interconnected binary counters, each binary counter having a plurality of stages; counter stage output means coupled to each of said plurality of stages for providing output signals representative of the state of each said stage, a source of clock signals coupled to said binary counters for permitting said counters, a plurality of 1-of-n decoders coupled to said binary counters, each having a plurality of decoding inputs, a plurality of enabling inputs and a plurality of scanning outputs, first circuit means coupled between said counter stage output means of said first binary counter and said decoding inputs of each of said decoders for applying said signals representative of the state of each counter stage to said decoders; and, second circuit means coupled between at least one of said counter stage output means of said second binary counter and said enabling inputs of each of said decoders for sequentially enabling said plurality of decoders, whereby said scanning outputs of said plurality of decoders are sequentially scanned as said clock signals are applied to said binary counters.
Claim 3
Dependent Claim
32 words
A multiple position scanning circuit as in claim 1, further comprising: reset circuit means coupled to said first and second binary counters for resetting said counters upon completion of a scanning cycle.
Claim 4
Dependent Claim
58 words
A multiple position scanning circuit as in claim 1, further comprising: a utilization device coupled to said scanning outputs of said decoders to be scanned thereby; and, clock start circuit means coupled between said utilization device and said source of clock signals for starting said source of clock signals in response to a signal from said utilization device.
Claim 5
Dependent Claim
92 words
A multiple position scanning circuit as in claim 1, wherein: four 1-of-n decoders are provided; and, wherein both said enabling inputs of one said decoder are coupled directly to counter stage output means of said second binary counter, both said enabling inputs of a second one of said decoders are coupled through inverters to said counter stage output means of said second binary counter, and one of said enabling inputs of each of the remaining decoders is coupled through an inverter to said counter stage output means of said second binary counter.
Claim 6
Dependent Claim
128 words
A network for scanning a predetermined number of data positions in a utilization device comprising: first means for supplying a sequence of pulses in a binary code, second means for supplying a sequence of pulses in a binary code, a plurality of 1-of-n decoders, each having a plurality of decoding inputs coupled to said first means, a plurality of scanning outputs for coupling to said utilization device, and a pair of enabling inputs for coupling to said second means; a separate logic circuit means for coupling said pairs of enabling inputs of each of said decoders with said second means for sequentially enabling said plurality of decoders; and, a plurality of auxiliary logic circuit means coupled to said first and second means for providing an auxiliary scanning capacity.
Claim 7
Dependent Claim
128 words
A network for scanning a predetermined number of data positions in a utilization device comprising: first means for supplying a sequence of pulses in a binary code, second means for supplying a sequence of pulses in a binary code, a plurality of 1-of-n decoders, each having a plurality of decoding inputs coupled to said first means, a plurality of scanning outputs for coupling to said utilization device, and a pair of enabling inputs for coupling to said second means; a separate logic circuit means for coupling said pairs of enabling inputs of each of said decoders with said second means for sequentially enabling said plurality of decoders; and, a plurality of auxiliary logic circuit means coupled to said first and second means for providing an auxiliary scanning capacity.
Claim 8
Dependent Claim
28 words
A network for scanning a predetermined number of data positions in a utilization device as in claim 5, wherein: said second means comprises a multiple stage binary counter.
Claim 9
Dependent Claim
68 words
A multiple position scanning circuit as in claim 6, wherein: one of said separate logic circuit means includes a two input NOR gate coupled at its output to both inputs of one of said decoders, and having a second NOR gate and an inverter coupled to its input, and wherein stages of said binary counter are coupled to the inputs of said second NOR gate and said inverter.
Claim 10
Dependent Claim
63 words
A multiple position scanning circuit as in claim 6, wherein: one of said separate logic circuit means includes an inverter coupled to one of said enable inputs of one of said decoders, said inverter having a NOR gate coupled to its input, and wherein said NOR gate includes a plurality of inputs which are coupled to stages of said multiple stage binary counter.
Claim 11
Dependent Claim
48 words
A multiple position scanning circuit as in claim 5, wherein: said plurality of auxiliary logic circuit means include a pair of separate multiple input logic gates having said inputs thereof coupled to said first and second means, and having outputs adapted to be coupled to said utilization device.
Claim 12
Dependent Claim
39 words
A multiple position scanning circuit as in claim 5, wherein: said first and second means comprise multiple stage binary counters coupled together so that said second means is actuated only after said first means has reached its counting capacity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-02-03 | 1978-08-05 | 1979-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-02-03 | 1982-08-05 | 1983-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-02-03 | 1986-08-05 | 1987-02-04 | $7700.00 | Window Closed / Lapsed |