Line control circuit

Claim 2

An improved line circuit arrangement for use in conjunction with multi-stage switching networks, said arrangement including a plurality of line circuits, at least some of said line circuits connected to a first stage switching matrix of the multi-stage switching network over a first multiple, at least some of said line circuits including detector means connected to said first multiple operating to determine when a path is switched through said switching network, said detector means operative when the telephone associated with a line circuit having a detector means is in the off hook or the on hook condition, making means operated responsive to the operation of said detector means for marking said first multiple, and said marking means comprising a constant current source common to a plurality of said line circuits.

Claim 3

The improved line circuit arrangement of claim 1 including means for normally holding said first multiple at approximately ground level until said network is switched through.

Claim 4

The improved line circuit arrangement of claim 1 wherein determining means are provided for determining when the telephone set associated with said line circuit presents a request for service signal.

Claim 5

The improved line circuit arrangement of claim 1 wherein said detector means comprises a first transistor coupled to said first multiple in a manner so that it conducts when the network is not switched through and is turned off responsive to a path being switched through the network.

Claim 6

The improved line circuit arrangement of claim 4 wherein capacitor timing means are provided for varying the slope of the marking signal produced by said marking means.

Claim 7

The improved line circuit arrangement of claim 1 wherein switching means are provided between said constant current source and said first multiple.

Claim 8

The improved line circuit arrangement of claim 6 wherein said switching means cOmprises a constant current control transistor that is normally off, and said constant current control transistor being switched to the conducting state by a mark pulse.

Claim 9

The improved line circuit arrangement of claim 7 wherein means are provided responsive to dial pulses for grounding said first multiple.

Claim 10

A path selecting system for selecting a path from an input circuit requesting service to an allotted output circuit through a multi-stage network, each of said stages comprising a plurality of matrices, each of said matrices comprising a plurality of overlapping input and output multiples, means for linking the output multiples of the preceding stages to the input multiples of the succeeding stages, means for linking each of the plurality of said input circuits to at least one input multiple of the first of said stages, means for linking each of a plurality of said output circuits to at least one output multiple of the last of said stages, solid state cross point elements coupled between said input and said output multiples at the points of overlapping, said cross point elements capable of being switched between a conducting state and a non-conducting state to interconnect said overlapping multiples in the conducting state and to disconnect said overlapping multiples in the non-conducting state, a control circiut attached to each output multiple linked to a succeeding stage, said control circuit selectively enabling said cross point switching elements, said enabling means operated responsive to said control circuit being allotted, said input circuits comprising line circuits, said line circuits having means for applying a marking signal to the input multiples to which said line circuits are attached to operate cross point elements connected thereto which are enabled, and said marking means including a constant current derived from a source common to a plurality of said line circuits.

Claim 11

A path selecting system for selecting a path from an input circuit requesting service to an allotted output circuit through a multi-stage network, each of said stages comprising a plurality of matrices, each of said matrices comprising a plurality of overlapping input and output multiples, means for linking the output multiples of the preceding stages to the input multiples of the succeeding stages, means for linking each of the plurality of said input circuits to at least one input multiple of the first of said stages, means for linking each of a plurality of said output circuits to at least one output multiple of the last of said stages, solid state cross point elements coupled between said input and said output multiples at the points of overlapping, said cross point elements capable of being switched between a conducting state and a non-conducting state to interconnect said overlapping multiples in the conducting state and to disconnect said overlapping multiples in the non-conducting state, a control circiut attached to each output multiple linked to a succeeding stage, said control circuit selectively enabling said cross point switching elements, said enabling means operated responsive to said control circuit being allotted, said input circuits comprising line circuits, said line circuits having means for applying a marking signal to the input multiples to which said line circuits are attached to operate cross point elements connected thereto which are enabled, and said marking means including a constant current derived from a source common to a plurality of said line circuits.