Receiver for dfsk signals

Claim 2

Apparatus for receiving a DFSK signal composed of intervals of f1, f2, f3 or f4 which represent progressively higher frequencies and designate mark or space signals on a pair of canals comprising in combination means for detecting said DFSK signals and for producing therefrom a DC signal whose amplitude is proportional to the frequencies of said DFSK signal; means for establishing first, second and third reference voltage levels from the DC signals produced from f1 and f4, said first, second and third levels being between the amplitudes of the DC signals produced from f1 and f2, f2 and f3, and f3 and f4, respectively; means for developing a binary signal indicative of the number of said lEvels that are exceeded by the DFSK signal being detected; and means for converting said binary signal into two mark or space signals.

Claim 3

In an arrangement as defined in claim 1 wherein said means for producing said DC signal comprises a phase locked loop functioning as a frequency discriminator.

Claim 4

In an arrangement as defined in claim 1 wherein said frequencies f1, f2, f3 and f4 are separated by equal audio frequency amounts.

Claim 5

In an arrangement as defined in claim 1 wherein said first, second and third levels are midway between the amplitudes of the DC signals produced from f1 and f2, f2 and f3 and f3 and f4.

Claim 6

In an arrangement as defined in claim 1 wherein said means for developing said binary signal comprises three comparators, one input of each comparator having applied thereto the DC signal produced from the DFSK signal, the other input of each comparator being a different one of said reference levels, each of said comparators wherein said DC signal exceeds said reference level producing an output signal which forms one bit of said binary signal.

Claim 7

In an arrangement as defined in claim 1 further comprising a register; means for feeding said two mark or space signals to said register; and means for transferring said two mark or space signals from said register to a pair of output canals a pre-selected time after the occurrence of a frequency transition in said DFSK signal.

Claim 8

In an arrangement as defined in claim 1 further comprising means for detecting any change in the frequency of said detected DFSK signal; and means for feeding said two mark or space signals to said pair of canals a predetermined time after this detected change.

Claim 9

In an arrangement as defined in claim 1 wherein said means for establishing said reference levels includes a pair of peak detectors, one of said detectors being responsive to f4 producing a DC output voltage whose magnitude is proportional thereto, the other of said detectors being responsive to f1 and producing a DC output voltage whose magnitude is proportional thereto.

Claim 10

In an arrangement as defined in claim 8 wherein said means for establishing said reference levels further includes a potentiometer; means for applying the Dc output voltages from said pair of detectors to opposite ends of said potentiometer, said potentiometer having three output taps which are located at the 1/6, 1/2 and 5/6 resistance points, the voltages available at said output taps corresponding to said reference levels.

Claim 11

A receiver for double frequency shift keying signals made up of f1, f2, f3 or f4 states which represent progressively higher frequency and designate mark or space conditions on a pair of output canals comprising means for detecting said DFSK signal and for developing therefrom a DC signal whose amplitude is proportional to the frequency of said detected DFSK signal; means for comparing said DC signal with three threshold levels which are midway between two DC signals produced from f1 and f2, from f2 and f3 and from f3 and f4, respectively, and for generating three signals which are indicative of the number of threshold levels that are exceeded by the detected DFSK signal; means for converting said three signals into the two designated mark or space signals represented by said DFSK signal; a register; means for feeding said two mark or space signals to said register; and means for transferring said mark or space signals from said register to said pair of canals only after a predetermined time interval has elapsed following a frequency shift in said detected DFSK signal.

Claim 12

A receiver for double frequency shift keying signals made up of f1, f2, f3 or f4 states which represent progressively higher frequency and designate mark or space conditions on a pair of output canals comprising means for detecting said DFSK signal and for developing therefrom a DC signal whose amplitude is proportional to the frequency of said detected DFSK signal; means for comparing said DC signal with three threshold levels which are midway between two DC signals produced from f1 and f2, from f2 and f3 and from f3 and f4, respectively, and for generating three signals which are indicative of the number of threshold levels that are exceeded by the detected DFSK signal; means for converting said three signals into the two designated mark or space signals represented by said DFSK signal; a register; means for feeding said two mark or space signals to said register; and means for transferring said mark or space signals from said register to said pair of canals only after a predetermined time interval has elapsed following a frequency shift in said detected DFSK signal.