Method for fabricating semiconductor devices utilizing composite masking

Claim 2

IN A METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE, THE STEPS COMPRISING: FORMING A FIRST LAYER COMPRISING SILICON DIOXIDE ON A SURFACE OF BODY OF SILICON SEMICONDURCOTR MATERIAL, FORMING A PRESELECTED PATTERN OF OPENINGS IN SAID FIRST LAYER TO EXPOSED PRESELECTED REGIONS OF SAID SILICON MATERIAL, SAID EXPOSED PORTIONS BEING PRECISELY SPACED WITH RESPECT TO ONE ANOTHER TO DEFINE A COMPOSITE DIFFUSION MASK, FORMING A SECOND LAYER COMPRISING SILICON NITRIDE ON SAID EXPOSED SILICON REGIONS AND ON SAID COMPOSITE DIFFUSION MASK,

Claim 3

A method as in claim 1 wherein said device is an integrated circuit, wherein the first doping step forms isolation regions, and wherein the second doping step forms transistor base regions.

Claim 4

A method for selectively exposing accurately spaced surface regions of a semiconductor substrate as set forth in claim 1 wherein the step of forming said third layer is characterized by converting a portion of said second layer to silicon dioxide having a thickness substantially less than either said first layer or said second layer, thereby enabling increased geometric resolution during the step of forming said openings in said third layer.

Claim 5

A method in accordance with claim 1 wherein the step of forming said third layer is characterized by controlling the thickness thereof to be at least five times less than either said first silicon dioxide layer or said silicon nitride layer.

Claim 6

A method for selectively exposing accurately spaced surface regions of a semiconductor substrate as set forth in claim 1 wherein the steps of patterning said silicon nitride layers are characterized by selectively etching apertures therethrough, said apertures being substantially larger than the respective corresponding apertures through said first layer, and in general alignment therewith, whereby alignment tolerances in patterning said nitride layers are materially reduced.

Claim 7

In a method for fabricating a semiconductor device, the steps comprising: a. forming a first layer comprising silicon dioxide on a surface of a body of silicon semiconductor material; b. forming a preselected pattern of openings in said first layer through a mask to expose preselected regions of said silicon material, said exposed portions being precisely spaced with respect to one another to define a composite diffusion mask; c. forming a second layer comprising silicon nitride on said exposed silicon regions and composite diffusion mask; d. forming a third layer comprising silicon dioxide on said silicon nitride layer; e. forming a first preselected pattern of openings in said third layer to expose preselected regions oF said silicon nitride layer whereby said third layer defines an etchant mask, said exposed preselected regions of said silicon nitride layer being formed in registry with a first set of said openings in said first layer; f. removing said exposed regions of said silicon nitride layer to define apertures therethrough, said apertured second layer defining a diffusion mask; g. doping the preselected regions at the surface of the body of semiconductor material exposed by said apertures in said second layer with conductivity-type determining impurities to form regions of preselected conductivity-type in the body of semiconductor material; h. forming a fourth layer comprising silicon nitride over the resultant structure; i. forming a fifth layer comprising silicon dioxide over said fourth layer; j. patterning said fifth layer to define a second preselected pattern of openings corresponding with a second set of said openings in said first layer; k. removing portions of said fourth layer exposed by said second pattern of openings, thereby exposing a second set of locations at the surface of said substrate; and l. doping said second set of locations with impurities.

Claim 8

In a method for fabricating a semiconductor device, the steps comprising: a. forming a first layer comprising silicon dioxide on a surface of a body of silicon semiconductor material; b. forming a preselected pattern of openings in said first layer through a mask to expose preselected regions of said silicon material, said exposed portions being precisely spaced with respect to one another to define a composite diffusion mask; c. forming a second layer comprising silicon nitride on said exposed silicon regions and composite diffusion mask; d. forming a third layer comprising silicon dioxide on said silicon nitride layer; e. forming a first preselected pattern of openings in said third layer to expose preselected regions oF said silicon nitride layer whereby said third layer defines an etchant mask, said exposed preselected regions of said silicon nitride layer being formed in registry with a first set of said openings in said first layer; f. removing said exposed regions of said silicon nitride layer to define apertures therethrough, said apertured second layer defining a diffusion mask; g. doping the preselected regions at the surface of the body of semiconductor material exposed by said apertures in said second layer with conductivity-type determining impurities to form regions of preselected conductivity-type in the body of semiconductor material; h. forming a fourth layer comprising silicon nitride over the resultant structure; i. forming a fifth layer comprising silicon dioxide over said fourth layer; j. patterning said fifth layer to define a second preselected pattern of openings corresponding with a second set of said openings in said first layer; k. removing portions of said fourth layer exposed by said second pattern of openings, thereby exposing a second set of locations at the surface of said substrate; and l. doping said second set of locations with impurities.

Claim 9

A method in accordance with claim 6 wherein said third layer is approximately one order of magnitude thinner than either said first layer or said second layer.

Claim 10

A method in accordance with claim 7 wherein said exposed portions of said silicon nitride layer are removed by exposing said etchant mask to a preselected etchant which reacts with silicon nitride at a substantially faster rate than it reacts with silicon dioxide.